Abstract: Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.

Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

Abstract: Various embodiments include approaches for designing three-dimensional (3D) integrated circuits (ICs). In one embodiment, a system is configured to: read an electronic chip identification (ECID) for a plurality of dies formed from distinct wafer lots, the ECID indicating a process performance parameter for each distinct wafer lot; create a reference table mapping a back-bias voltage to be applied to each die to the process performance parameter for each distinct wafer lot; determine performance requirements of a customer design for the 3D IC structure; assemble the design of the 3D IC structure including a set of dies selected from at least two of the distinct wafer lots; and assign a back bias voltage to each die based upon the performance requirements of the customer design and the reference table.

Abstract: Method of burn-in power optimization which includes: testing integrated circuit devices to record a performance speed for each of the integrated circuit devices; categorizing each integrated circuit device by a selective voltage binning (SVB) process into a voltage bin according to the performance speed of the integrated circuit device; performing a burn-in operation on each of the integrated circuit devices while toggling an SVB performance monitor on each of the integrated circuit devices; testing the plurality of integrated circuit devices after the burn-in operation; categorizing each integrated circuit device into the SVB voltage bin according to the performance speed of the integrated circuit device after the burn-in operation; when the SVB voltage bin after the burn-in operation corresponds to an SVB voltage bin having a slower performance speed than before the burn-in operation, changing the SVB voltage bin to the slower performance speed.

Abstract: Systems and methods for reducing hot spots and recovering Vt/area to improve chip performance in an integrated circuit design. According to the method, physical grid areas for an IC chip are defined and a switching window for library elements of an integrated circuit design in a region of the chip is determined. Points of peak current for library elements within the switching window are determined. A grid area is selected and library elements having additional usable timing margin are identified. The library elements are prioritized, based on location in the grid area according to peak current and usable timing margin. Based on order of priority, the timing of signal paths in the grid area may be adjusted in order to misalign points of peak current and maintain current density in the region below a threshold and/or a library element within the grid area may be changed to recover area within the grid area.

Abstract: Various embodiments include approaches for designing three-dimensional (3D) integrated circuits (ICs). In one embodiment, a system is configured to: read an electronic chip identification (ECID) for a plurality of dies formed from distinct wafer lots, the ECID indicating a process performance parameter for each distinct wafer lot; create a reference table mapping a back-bias voltage to be applied to each die to the process performance parameter for each distinct wafer lot; determine performance requirements of a customer design for the 3D IC structure; assemble the design of the 3D IC structure including a set of dies selected from at least two of the distinct wafer lots; and assign a back bias voltage to each die based upon the performance requirements of the customer design and the reference table.

Abstract: Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.

Abstract: Disclosed is a method for performing reliability qualification of manufactured integrated circuit (IC) chips. In the method, IC chips are manufactured according to a design and sorted into groups, which correspond to different process windows within a process distribution for the design. Group fail rates are determined for the groups. Reliability qualification of the manufactured IC chips is performed. Specifically, a sample of the IC chips is stress tested and the manufactured IC chips are qualified if the actual fail rate of the sample is no greater than an expected fail rate. The expected fail rate used is not, however, the expected overall fail rate for all the manufactured IC chips. Instead it is a unique expected fail rate for the specific sample itself and it is determined considering fail rate contributions from only those specific groups of IC chips from which the IC chips in the sample were selected.

Abstract: Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax.

Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products that provide for area and/or power optimization through post-layout modification of design blocks. Specifically, a layout for an initial IC design is accessed. This initial IC design incorporates multiple instances of the same design block. Each instance includes a primary input connected to top-level logic for receiving a signal and one or more modifiable periphery sections. A timing analysis is performed to close timing and determine arrival times of the signal at the primary inputs of all instances of the design block, respectively, given the layout. The arrival times are then compared to a preselected threshold arrival time and the modifiable periphery section(s) of any specific instance of the design block having an arrival time that is equal to or less than the preselected threshold arrival time is selectively modified in order to generate an area and/or power optimized integrated circuit design.

Abstract: Disclosed is an integrated circuit (IC) chip having an on-chip usable life depletion meter. This meter incorporates programmable bits, which represent units of usable life. These programmable bits are sequentially ordered from an initial programmable bit to a last programmable bit and are automatically programmed in order, as the expected usable life of the IC chip is depleted. These programmable bits are readable to determine the remaining usable life of the IC chip. Also disclosed is a method that uses the on-chip usable life depletion meter. In the method, the remaining usable life of an IC chip, once known, is used either as the basis for allowing re-use of the IC chip (e.g., for a non-critical application and when the remaining usable life is sufficient) or as the basis for preventing re-use of the IC chip (e.g., for a critical application or when the remaining usable life is insufficient).

Abstract: Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax.

Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

Abstract: Methods and structures for leakage screening are disclosed. A method includes sorting devices manufactured from the same device design into voltage bins corresponding to a respective supply voltage. The method further includes determining a respective total power of each of the voltage bins. The method further includes determining a respective uplift power of the voltage bins. The method further includes determining a respective first leakage screen value for each of the voltage bins based on the respective uplift power of each of the voltage bins.

Abstract: Disclosed are temperature-aware integrated circuit (IC) design methods and systems, which establish a customized power delivery network (PDN) for an IC early in the design process in order to generate, in a timely manner, a final IC design layout that can be used to manufacture IC chips that will exhibit minimal hotspots. Specifically, prior to placement of library elements, an initial PDN is established and divided into sections. The library elements are placed. Then, potential hotspots associated with any of the sections are identified and a customized PDN for the IC is established to eliminate the hotspots. That is, for each section, a total power consumption amount is determined. When the total power consumption amount is greater than the threshold, a hotspot is indicated and the section is customized to eliminate the hotspot. Also disclosed is a resulting IC chip structure.

Abstract: Disclosed is a method wherein selective voltage binning and leakage power screening of integrated circuit (IC) chips are performed. Additionally, pre-test power-optimized bin reassignments are made on a chip-by-chip basis. Specifically, a leakage power measurement of an IC chip selected from a voltage bin can is compared to a bin-specific leakage power screen value of the next slower voltage bin. If the leakage power measurement is higher, the IC chip will be left in the voltage bin to which it is currently assigned. If the leakage power measurement is lower, the IC chip will be reassigned to that next slower voltage bin. These processes can be iteratively repeated until no slower voltage bins are available or the IC chip cannot be reassigned. IC chips can subsequently be tested according to testing parameters, including the minimum test voltages, associated with the voltage bins to which they are finally assigned.

Abstract: Disclosed are electromigration (EM)-aware integrated circuit (IC) design techniques, which consider EM early in the IC design process in order to generate, in a timely manner, an IC design that can be used to manufacture IC chips that will exhibit minimal EM fails for improved IC reliability. Specifically, prior to placement of library elements, EM-relevant information is acquired and used to define protected zones around at least some of the library elements. Once the protected zones are defined, the library elements are placed relative to power rails in a previously designed power delivery network (PDN) and this placement process is performed such that each library element is prevented from being placed in a protected zone around any other library element to avoid EM fails in the PDN. Optionally, this same EM-relevant information is used during subsequent synthesis of a clock distribution network to prevent EM fails therein.

Abstract: Disclosed are integrated circuit (IC) design methods, systems and computer program products that provide for area and/or power optimization through post-layout modification of design blocks. Specifically, a layout for an initial IC design is accessed. This initial IC design incorporates multiple instances of the same design block. Each instance includes a primary input connected to top-level logic for receiving a signal and one or more modifiable periphery sections. A timing analysis is performed to close timing and determine arrival times of the signal at the primary inputs of all instances of the design block, respectively, given the layout. The arrival times are then compared to a preselected threshold arrival time and the modifiable periphery section(s) of any specific instance of the design block having an arrival time that is equal to or less than the preselected threshold arrival time is selectively modified in order to generate an area and/or power optimized integrated circuit design.

Abstract: Disclosed herein are methods for making integrated circuit (IC) chip reliability estimations based on resistance measurements and for using such estimations to disposition manufactured chips. In the methods, a resistance-to-electromigration fail rate correlation can be empirically determined for an integrated circuit chip design. Additionally, for each chip manufactured according to the design, at least one resistance monitor can be used to acquire a resistance value for that manufactured chip. Then, given the resistance value and the resistance-to-electromigration fail rate correlation, the expected reliability of the manufactured chip can be estimated and the manufactured chip can be dispositioned in a variety of different ways.

Abstract: Method of burn-in power optimization which includes: testing integrated circuit devices to record a performance speed for each of the integrated circuit devices; categorizing each integrated circuit device by a selective voltage binning (SVB) process into a voltage bin according to the performance speed of the integrated circuit device; performing a burn-in operation on each of the integrated circuit devices while toggling an SVB performance monitor on each of the integrated circuit devices; testing the plurality of integrated circuit devices after the burn-in operation; categorizing each integrated circuit device into the SVB voltage bin according to the performance speed of the integrated circuit device after the burn-in operation; when the SVB voltage bin after the burn-in operation corresponds to an SVB voltage bin having a slower performance speed than before the burn-in operation, changing the SVB voltage bin to the slower performance speed.