Abstract: Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window. The method further includes determining at least one failure mechanism for each bin assignment. The method further includes generating different reliability models when the at least one failure mechanism is a function of the process window, and generating common reliability models when the at least one failure mechanism is not the function of the process window. The method further includes identifying at least one risk factor for each bin assignment, and generating aggregate models using a manufacturing line distribution. The method further includes determining a fail rate by bin and optimizing a line center to minimize product fail rate. The method further includes determining a fail rate by bin and scrapping production as a function of a manufacturing line excursion event.

Abstract: Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters.

Abstract: Systems and methods for selective voltage binning within a three-dimensional integrated chip stack. A method is provided that includes defining a correlation between at least two parameters. At least one parameter of the at least two parameters is from a first chip of a three-dimensional integrated chip stack and at least one parameter of the at least two parameters is from a second chip of the three-dimensional integrated chip stack. The method further includes generating a covariance matrix based on the at least two parameters. The method further includes calculating a new parameter or new parameter set using the covariance matrix. The method further includes performing statistical static timing analysis (SSTA) such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes determining whether timing targets for the three-dimensional integrated chip stack are achieved.

Abstract: A method of optimizing power and timing for an integrated circuit (IC) chip, which uses an IC technology that exhibits temperature inversion, by modifying a voltage supplied to the IC chip, while meeting power consumption and timing delay performances across lower and higher temperature ranges. A high voltage is selected that meets a closed timing analysis across a full temperature range to meet a timing performance and a low voltage is selected to meet the timing performance and the power performance across a lower temperature range to a temperature cut point in the higher temperature range. The IC chip is turned on at the high voltage and the high voltage is lowered to the low voltage when the temperature cut point is exceeded to meet the power performance while maintaining the timing performance.

Abstract: Disclosed are integrated circuit design systems and methods, wherein selected functional library elements are placed in a layout to meet product specifications and selected hybrid fill-placeable library elements are placed in that same layout to meet at least one feature density rule. Each hybrid fill-placeable library element comprises fill shapes corresponding to specific features subject to a density rule and a marker shape that provides an instruction to ignore any density rule violations within that element for purposes of design rule checking. Placement of the hybrid fill-placeable library elements is performed to balance out density rule violations in functional library elements elsewhere in the layout, thereby avoiding the need for post-processing of the completed IC design to add fill shapes.

Abstract: A method of optimizing power and timing for an integrated circuit (IC) chip, identifies a plurality of valid temperature and voltage combinations that allow integrated circuit chips produced according to the integrated circuit chip design to operate within average power consumption goals and timing delay goals. Such a method selects temperature cut points from the valid temperature and voltage combinations for each of the integrated circuit chips, calculates a power consumption amount of each of the temperature cut points, and adjusts the temperature cut points based on the power consumption amount until the temperature cut points achieve the average power consumption goals. Next, this method tests each of the integrated circuit chips, and records the temperature cut points in the memory of the integrated circuit chips.

Abstract: Methods determine temperature and voltage relationships for integrated circuit library elements to produce a continuous temperature-voltage function. Some of the library elements can be used or combined to form an integrated circuit design. Further, the performance characteristics for integrated circuit chips produced according to the integrated circuit design can be defined, such performance characteristics include an operating temperature range, etc. The continuous temperature-voltage function is applied to the performance characteristics to determine a plurality of temperature/voltage combinations for the integrated circuit chips. Each of the temperature/voltage combinations comprises an operating voltage for each operating temperature within the operating temperature range of the integrated circuit chips. Next, the integrated circuit chips are produced according to the integrated circuit design. The temperature/voltage combinations are recorded in memory of the integrated circuit chips.

Abstract: Systems and methods for selective voltage binning within a three-dimensional integrated chip stack. A method is provided that includes defining a correlation between at least two parameters. At least one parameter of the at least two parameters is from a first chip of a three-dimensional integrated chip stack and at least one parameter of the at least two parameters is from a second chip of the three-dimensional integrated chip stack. The method further includes generating a covariance matrix based on the at least two parameters. The method further includes calculating a new parameter or new parameter set using the covariance matrix. The method further includes performing statistical static timing analysis (SSTA) such that the new parameter or the new parameter set is propagated into the SSTA. The method further includes determining whether timing targets for the three-dimensional integrated chip stack are achieved.

Abstract: Methods determine temperature and voltage relationships for integrated circuit library elements to produce a continuous temperature-voltage function. Some of the library elements can be used or combined to form an integrated circuit design. Further, the performance characteristics for integrated circuit chips produced according to the integrated circuit design can be defined, such performance characteristics include an operating temperature range, etc. The continuous temperature-voltage function is applied to the performance characteristics to determine a plurality of temperature/voltage combinations for the integrated circuit chips. Each of the temperature/voltage combinations comprises an operating voltage for each operating temperature within the operating temperature range of the integrated circuit chips. Next, the integrated circuit chips are produced according to the integrated circuit design. The temperature/voltage combinations are recorded in memory of the integrated circuit chips.

Abstract: Methods and systems for multiple manufacturing line qualification are provided. A method includes establishing a product template and producing products on one or more manufacturing lines. The products include product macros placed on a chip. The method also includes establishing allowed parametric match from line to line. The method further includes determining that products from the one or more manufacturing lines meet the allowed parametric match.

Abstract: Methods and systems for semiconductor line scribe centering are provided. A method includes placing and measuring substantially identical test macros within a chip and in a scribe line. The method also includes establishing an estimate correlation between scribe line measurements taken during a manufacturing process and product measurements taken on a final product. The method also includes determining empirical scribe line specification limits consistent with established product screen limits. The method also includes adjusting the manufacturing process in order to optimize performance to the empirical scribe line specification limits.

Abstract: Approaches are provided for improving timing of new and existing semiconductor products. Specifically, a method is provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to set starting across chip variation assumptions using design rules. The programming instructions are further operable to design a test chip and/or product chip using the starting across chip variation assumptions to close timing of the design. The programming instructions are further operable to place devices in the test chip and/or product chip. The programming instructions are further operable to compare performance of the devices within the test chip and/or the product chip to the starting across chip variation assumptions. The programming instructions are further operable to adjust the starting across chip variation assumptions based on the measured performance of the test chip and/or the product chip.

Abstract: A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.

Abstract: Approaches for binning integrated circuits using timing are provided. A method includes performing a statistical timing analysis of a design. The method also includes identifying bin sub-spaces within a process space of the design. The method further includes determining a frequency limit for each said bin sub-space. The method additionally includes closing timing to the frequency limit for each said bin sub-space.

Abstract: Methods and structures for leakage screening are disclosed. A method includes sorting devices manufactured from the same device design into voltage bins corresponding to a respective supply voltage. The method further includes determining a respective total power of each of the voltage bins. The method further includes determining a respective uplift power of the voltage bins. The method further includes determining a respective first leakage screen value for each of the voltage bins based on the respective uplift power of each of the voltage bins.

Abstract: A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

Abstract: Methods and systems for systems and methods for product reliability estimation are provided. A method implemented in a computer infrastructure includes separating products into different process window segments. The method also includes calculating a product reliability estimation for each process window segment. The method further includes calculating a system product reliability estimation. At least one of the separating, calculating the product reliability estimation, and calculating the system product reliability estimation is performed using a processor.

Abstract: Methods and systems for system power estimation are provided. A method implemented in a computer infrastructure includes separating products into different segments. The method also includes calculating a power estimation for each segment based on operating conditions of each respective segment. The method further includes calculating an average system power estimation. At least one of the separating, calculating the power estimation, and calculating the average system power estimation is performed using a processor.

Abstract: Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.

Abstract: Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.