Abstract: In the systems and methods, an identifier is generated for a printed circuit board (PCB), chips are connected to the PCB, and corresponding sets of programmable bits on the chips are programmed to match specific sections of the identifier. Due to the generation of the identifier and the programming of the corresponding sets of programmable bits on the chips to match specific sections of the identifier, the validity of the chips can be verified at any time during product life. For example, for each chip, its set of programmable bits can be read and, then, a determination can be made as to whether that set of programmable bits is indeed programmed to match a specific section of the identifier. Operation of the PCB can be allowed when all the chips are determined to be valid and prohibited when any of the chips are determined to be invalid (e.g., previously used).

Abstract: Aspects of the present disclosure include a computer-implemented method for identifying an operating temperature of an integrated circuit (IC), the method including using a computing device for: applying a test voltage to a test circuit embedded within the IC, the test circuit including a phase shift memory (PSM) element therein, wherein the PSM element crystallizes at a crystallization temperature from an amorphous phase having a first electrical resistance into a crystalline phase having a second electrical resistance, the second electrical resistance being less than the first electrical resistance; and identifying the IC as having operated above the crystallization temperature in response to a resistance of the test circuit at the test voltage being outside of the target operating range.

Abstract: Disclosed is a computer system for system integration, wherein chip selection for a specific system is performance and reliability optimized and, thereby cost optimized. In the system, a memory stores a chip-level performance specification and a chip-level reliability specifications, each defined for a specific integrated circuit chip that is to be incorporated into a specific system. The memory also stores an inventory that references manufactured instances of the specific integrated circuit chip sorted into bins, which are associated with different performance process windows and which are assigned different reliability levels. A processor uses the inventory to select an instance of the specific integrated circuit chip from one of the bins for actual incorporation into the specific system and does so such that the chip-level performance specification and the chip-level reliability specification are met. Also disclosed are a method and a computer program product that can similarly perform system integration.

Abstract: Disclosed is a system that periodically increases the supply voltage applied to a power rail of an integrated circuit chip that is incorporated into a product, thereby compensating for age-dependent changes in a performance parameter sensitivity (e.g., in a delay sensitivity). In this system, the chip comprises at least a memory, an age monitor, a voltage selector and a power rail. The memory stores an age/voltage table. The age monitor automatically measures the age of the chip. Based on the age and using the age/voltage table, the voltage selector selects a specific supply voltage and outputs a voltage selection signal to an adjustable voltage regulator, which can apply (e.g., automatically or on-demand) that specific supply voltage to the power rail. Also disclosed is a method for regulating the power supplied to an integrated circuit chip, which is incorporated into a product, and a method for generating an age/voltage table.

Abstract: Systems and methods for improving timing closure of new and existing semiconductor products by balancing sensitivities. More specifically, a method is provided for that includes defining at least one set of correlated parameters for a semiconductor product, the at least one set of correlated parameters comprising a first parameter and a second parameter. The method further includes measuring performance of embedded devices within the semiconductor product. The method further includes closing timing of the semiconductor product using the measured performance of the semiconductor product. The closing the timing of the semiconductor product comprises calculating a sensitivity to the first parameter based on the measured performance of the embedded devices within the semiconductor product and balancing the sensitivity to the first parameter with a sensitivity to a second parameter such that timing degradation is shifted from the first parameter to the second parameter.

Abstract: Disclosed is a computer system for system integration, wherein chip selection for a specific system is performance and reliability optimized and, thereby cost optimized. In the system, a memory stores a chip-level performance specification and a chip-level reliability specifications, each defined for a specific integrated circuit chip that is to be incorporated into a specific system. The memory also stores an inventory that references manufactured instances of the specific integrated circuit chip sorted into bins, which are associated with different performance process windows and which are assigned different reliability levels. A processor uses the inventory to select an instance of the specific integrated circuit chip from one of the bins for actual incorporation into the specific system and does so such that the chip-level performance specification and the chip-level reliability specification are met. Also disclosed are a method and a computer program product that can similarly perform system integration.

Abstract: In an approach to predicting reliability of semiconductor devices, one or more computer processors retrieve a first reliability prediction associated with a first reliability model. The one or more computer processors retrieve manufacturing reliability assessment data for a first manufacturing vintage of semiconductor devices. The one or more computer processors retrieve failure mechanism identification data associated with the manufacturing reliability assessment data. The one or more computer processors determine, based, at least in part, on the manufacturing reliability assessment data and associated failure mechanism identification data, a second reliability prediction. The one or more computer processors determine whether the second reliability prediction matches the first reliability prediction. Responsive to determining the second reliability prediction does not match the first reliability prediction, the one or more computer processors update the first reliability model.

Abstract: Methods and systems are provided for that are designed to impose an n-type to p-type device skew constraint that is beyond what normal technology limits allow in order to operate semiconductor devices at lower voltages while still achieving a similar performance at a lower power. More specifically, a method is provided for that includes setting device skew requirements for at least one library element, setting device skew test dispositions for the at least one library element based on the set device skew requirements, designing the at least one library element using device skew assumptions, fabricating the at least one library element on a product that includes at least one device skew monitor, determining an actual device skew of the fabricated at least one library element using the at least one device skew monitor, and determining whether the fabricated product meets target specifications.

Abstract: A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

Abstract: Methods and systems for system power estimation are provided. A method implemented in a computer infrastructure includes separating products into different segments. The method also includes calculating a power estimation for each segment based on operating conditions of each respective segment. The method further includes calculating an average system power estimation. At least one of the separating, calculating the power estimation, and calculating the average system power estimation is performed using a processor.

Abstract: Methods and systems are provided for that are designed to impose an n-type to p-type device skew constraint that is beyond what normal technology limits allow in order to operate semiconductor devices at lower voltages while still achieving a similar performance at a lower power. More specifically, a method is provided for that includes setting device skew requirements for at least one library element, setting device skew test dispositions for the at least one library element based on the set device skew requirements, designing the at least one library element using device skew assumptions, fabricating the at least one library element on a product that includes at least one device skew monitor, determining an actual device skew of the fabricated at least one library element using the at least one device skew monitor, and determining whether the fabricated product meets target specifications.

Abstract: Systems and methods for improving timing closure of new and existing semiconductor products by balancing sensitivities. More specifically, a method is provided for that includes defining at least one set of correlated parameters for a semiconductor product, the at least one set of correlated parameters comprising a first parameter and a second parameter. The method further includes measuring performance of embedded devices within the semiconductor product. The method further includes closing timing of the semiconductor product using the measured performance of the semiconductor product. The closing the timing of the semiconductor product comprises calculating a sensitivity to the first parameter based on the measured performance of the embedded devices within the semiconductor product and balancing the sensitivity to the first parameter with a sensitivity to a second parameter such that timing degradation is shifted from the first parameter to the second parameter.

Abstract: Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters.

Abstract: Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window. The method further includes determining at least one failure mechanism for each bin assignment. The method further includes generating different reliability models when the at least one failure mechanism is a function of the process window, and generating common reliability models when the at least one failure mechanism is not the function of the process window. The method further includes identifying at least one risk factor for each bin assignment, and generating aggregate models using a manufacturing line distribution. The method further includes determining a fail rate by bin and optimizing a line center to minimize product fail rate. The method further includes determining a fail rate by bin and scrapping production as a function of a manufacturing line excursion event.

Abstract: Disclosed are embodiments of a method, system and computer program product for optimizing integrated circuit product yield by re-centering the manufacturing line and, optionally, adjusting wafer-level chip dispositioning rules based on the results of post-manufacture (e.g., wafer-level or module-level) performance path testing. In the embodiments, a correlation is made between in-line parameter measurements and performance measurements acquired during the post-manufacture performance path testing. Then, based on this correlation, the manufacturing line can be re-centered. Optionally, an additional correlation is made between performance measurements acquired during wafer-level performance testing and performance measurements acquired particularly during module-level performance path testing and, based on this additional correlation, adjustments can be made to the wafer-level chip dispositioning rules to further minimize yield loss.

Abstract: Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window. The method further includes determining at least one failure mechanism for each bin assignment. The method further includes generating different reliability models when the at least one failure mechanism is a function of the process window, and generating common reliability models when the at least one failure mechanism is not the function of the process window. The method further includes identifying at least one risk factor for each bin assignment, and generating aggregate models using a manufacturing line distribution. The method further includes determining a fail rate by bin and optimizing a line center to minimize product fail rate. The method further includes determining a fail rate by bin and scrapping production as a function of a manufacturing line excursion event.

Abstract: Approaches are provided for improving timing of new and existing semiconductor products. Specifically, a method is provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to set starting across chip variation assumptions using design rules. The programming instructions are further operable to design a test chip and/or product chip using the starting across chip variation assumptions to close timing of the design. The programming instructions are further operable to place devices in the test chip and/or product chip. The programming instructions are further operable to compare performance of the devices within the test chip and/or the product chip to the starting across chip variation assumptions. The programming instructions are further operable to adjust the starting across chip variation assumptions based on the measured performance of the test chip and/or the product chip.

Abstract: A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.

Abstract: Methods and systems for qualifying a single cell with product path delay analysis are provided. A method includes designing a product using a model from an initial test site. The method also includes creating performance path tests for one or more paths on the product. The method further includes measuring performance path parameters of the product. The method includes determining that the measured performance path parameters match predicted performance path parameters.

Abstract: Systems and methods for semiconductor device reliability qualification during semiconductor device design. A method is provided that includes defining performance process window bins for a performance window. The method further includes determining at least one failure mechanism for each bin assignment. The method further includes generating different reliability models when the at least one failure mechanism is a function of the process window, and generating common reliability models when the at least one failure mechanism is not the function of the process window. The method further includes identifying at least one risk factor for each bin assignment, and generating aggregate models using a manufacturing line distribution. The method further includes determining a fail rate by bin and optimizing a line center to minimize product fail rate. The method further includes determining a fail rate by bin and scrapping production as a function of a manufacturing line excursion event.