Abstract: A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed.

Abstract: A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.

Abstract: A method of integrated circuit design and, more particularly, a method and system to optimize semiconductor products for power, performance, noise, die area, and cost through use of variable power supply voltage compression. The method is implemented in a computer-based tool and includes: embedding relationships in an optimization tool running on a computing device, wherein the relationships are based at least partly on performance, power-supply noise, die area, and power; inputting a set of product data and a set of technology data in the optimization tool running on the computing device; and determining product design parameters including power supply voltage, switching-noise-induced power supply voltage variation, and decap area. The determining is based on the relationships, the product data, and the technology data and is performed using the computing device running the optimization tool.

Abstract: Techniques, systems, and methods are provided for optimizing pattern density fill patterns for integrated circuits. The method includes adjusting an area of a scribe line and a density of dummy fill shapes in the adjusted scribe line, while maintaining an area of the die, to achieve a pattern density associated with technology ground rules for a particular design of the die.

Abstract: A method and system to predict a number of electromigration critical elements in semiconductor products. This method includes determining critical element factors for a plurality of library elements in a circuit design library using a design tool running on a computer device and based on at least one of an increased reliability temperature and an increased expected current. The method also includes determining a number of critical elements in a product based on: (i) numbers of respective ones of the plurality of library elements comprised in the product, and (ii) the critical element factors.

Abstract: A computer readable medium, system and associated method is provided for designing an integrated circuit with inserted loops. The method comprises the steps of inserting a loop with tagged wire segments and/or vias in a fully routed and DCR clean integrated circuit; performing a DRC; and fixing DRC violations by removing tagged wire segments and/or vias which contribute to a violation.

Abstract: A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

Abstract: An integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and Fourth wires form a path between the first and second wires redundant to the first via.

Abstract: Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the measurement structure on the multiple chip wafer using a reticle including the measurement structure between copies of the multiple chips on the reticle, wherein no one of the multiple chips covers an entirety of the reticle; performing the test on the multiple chip wafer using the measurement structure to acquire data across the reticle; using data from the performing to establish an across reticle variation model; and using the across reticle variation model to predict across chip variation for at least one of the multiple chips.

Abstract: A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

Abstract: Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and/or also to update supply chain forecasts.

Abstract: A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.

Abstract: A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed.

Abstract: A storage medium including a method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.

Abstract: A method of reliability evaluation and system fail warning using on chip parametric monitors. The method includes determining impact of parametric variation on reliability by identifying key parametric questions to be answered by stress, identifying parametric macros for each parameter, and identifying layout sensitive areas of evaluation. The process can also include a set of parametric macros in one of a test site or a product to be stressed, testing the set of parametric macros prior to start of stress and at each stress read out, and setting life time parameter profile for technology.

Abstract: Methods of modeling across reticle variations and a related reticle are disclosed. One embodiment of the method includes defining a test for determination across a multiple chip wafer; identifying a measurement structure for performing the test; implementing the measurement structure on the multiple chip wafer using a reticle including the measurement structure between copies of the multiple chips on the reticle, wherein no one of the multiple chips covers an entirety of the reticle; performing the test on the multiple chip wafer using the measurement structure to acquire data across the reticle; using data from the performing to establish an across reticle variation model; and using the across reticle variation model to predict across chip variation for at least one of the multiple chips.

Abstract: A method of estimating integrated circuit yield comprises providing an integrated circuit layout and a set of systematic defects based on a manufacturing process. Next, the method represents a systematic defect by modifying structures in the integrated circuit layout to create modified structures. More specifically, for short-circuit-causing defects, the method pre-expands the structures when the structures comprise a higher systematic defect sensitivity level, and pre-shrinks the structures when the structures comprise a lower systematic defect sensitivity level. Following this, a critical area analysis is performed on the integrated circuit layout using the modified structures, wherein dot-throwing, geometric expansion, or Voronoi diagrams are used. The method then computes a fault density value, random defects and systematic defects are computed.

Abstract: A computer readable medium, system and associated method is provided for designing an integrated circuit with inserted loops. The method comprises the steps of inserting a loop with tagged wire segments and/or vias in a fully routed and DCR clean integrated circuit; performing a DRC; and fixing DRC violations by removing tagged wire segments and/or vias which contribute to a violation.

Abstract: A method of modeling yield for semiconductor products includes determining expected faults for each of a plurality of library elements by running a critical area analysis on each of the library elements, and assessing, from the critical area analysis, an expected number of faults per unit area, and comparing the same to actual observed faults on previously manufactured semiconductor products. Thereafter, the expected number of faults for each library element is updated in response to observed yield. A database is established, which includes the die size and expected faults for each of the library elements. Integrated circuit product die size is estimated, and library elements to be used to create the integrated circuit die are selected. Fault and size data for each of the selected library elements are obtained, the adjusted estimated faults for each of the library elements are summed, and estimated yield is calculated.

Abstract: Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and/or also to update supply chain forecasts.