Abstract: A control apparatus of a GIO line includes a plurality of GIO line termination units, and a GIO control unit for generating a control signal to activate an operation of a specific one of the plurality of GIO termination units according to a data transmission method. Further, a method of controlling a GIO line through GIO termination includes the step of generating a control signal to activate an operation of a specific one of a plurality of GIO termination units according to a data transmission method.

Abstract: A memory device conducts a stable data access operation by removing glitch component in an internal clock outputted after a completion of self-refresh. This memory device includes a memory core region, a clock enable sensor for sensing an enable of a clock enable signal corresponding to a termination of a self-refresh operation to provide a sensing signal, a clock buffer for buffering a clock signal from the outside as an internal clock signal in response to the sensing signal and providing the internal clock signal to the memory core region, and a self-refresh control circuit for preventing a glitch component in the internal clock signal firstly outputted by the clock buffer in response to the sensing signal from transferring to the memory core region.

Abstract: An internal address generator for use in a semiconductor memory device includes an address detector, a drive pulse generator, and a delay unit. The address detector generates a comparison signal by comparing a first address currently input with a second address previously input. The drive pulse generator generates a drive pulse in response to the comparison signal. The delay unit outputs the first address as the second address and delays the second address to thereby generate an internal address synchronized with the drive pulse in case that the first address is different from the second address.

Abstract: A semiconductor memory device having a plurality of banks performs a refresh operation in sequence to each bank whether the refresh operation is required for all or less than all of the banks. The semiconductor memory device includes an extended mode register set containing a refresh information of each bank; and a bank refresh block for supporting a refresh operation performed in sequence to each bank in response to the refresh information of each bank.

Abstract: Provided is a memory device capable of automatically controlling a self refresh cycle by sensing an ambient temperature, rather than setting Extended Mode Register Set (EMRS) code. The memory device includes a temperature sensing unit for generating a first voltage independent of a temperature variation and a second voltage dependent upon a temperature variation, a comparing unit for comparing the first voltage with the second voltage to provide a comparison result signal, and a self refresh signal generating unit for receiving a self refresh entry signal and generating a self refresh signal of temperature compensated cycle under the control of the comparison result signal.

Abstract: An internal signal generator for use in a semiconductor memory device includes an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying an external address for a predetermined latency shorter than an additive latency set by the semiconductor memory device and selects one of the read delay addresses to thereby output an internal read address. The internal write address generation unit generates a plurality of write delay addresses by delaying the internal read address for a preset latency shorter than a column address strobe (CAS) latency set by the semiconductor memory device and selects one of the write delay addresses to thereby output an internal write address.

Abstract: A memory device conducts a stable data access operation by removing glitch component in an internal clock outputted after a completion of self-refresh. This memory device comprises a memory core region, a clock enable sensor for sensing an enable of a clock enable signal corresponding to a termination of a self-refresh operation to provide a sensing signal, a clock buffer for buffering a clock signal from the outside as an internal clock signal in response to the sensing signal and providing the internal clock signal to the memory core region, and a self-refresh control circuit for preventing a glitch component in the internal clock signal firstly outputted by the clock buffer in response to the sensing signal from transferring to the memory core region.