Abstract: A memory system may include: a nonvolatile memory device including a system region for storing lifespan information of a plurality of memory blocks and an one-Time Programmable (OTP) region which is not reset when firmware is upgraded; a function component configured to store the firmware; an interface configured to receive new firmware for upgrade; a validation control component configured to perform a validation operation of the nonvolatile memory device; and an upgrade component configured to upgrade the firmware when the validation operation of the nonvolatile memory device is performed, wherein the validation control component selects at least one backup block by referring to the OTP region, backs up the lifespan information to the at least one backup block, and then controls the upgrade component to upgrade the firmware.

Abstract: The storage device includes a memory device including a plurality of planes, and a memory controller configured to store, while the memory device is in a busy state, read requests for different planes among read requests for the memory device as read requests to be processed by the memory device after the busy state of the memory device is terminated.

Abstract: There are provided a memory controller and a memory system having the same. A memory controller includes: a command queue for queuing commands and outputting command information including Information of a previous command and a subsequent command; a command detector for outputting a detection signal according to the command information; and a command generator for generating the command and outputting a management command for managing a last command immediately following the previous command in response to the detection signal.

Abstract: A memory system includes: a memory device suitable for storing data; a history data generator suitable for generating history data having a plurality of physical memory block address data; and a history data analyzer suitable for detecting logical memory block address data in the history data.

Abstract: A memory system includes a memory device including a plurality of memory blocks, and a block management unit suitable for selecting a target super block and floating blocks from the memory blocks, matching blocks included in the target super block with the floating blocks, and changing the target super block to a super block.

Abstract: A controller includes a core suitable for transferring a plurality of requests; a buffer including a plurality of clusters; a buffer manager suitable for assigning the plurality of requests respectively into the plurality of clusters, and for storing storage information of the buffer and cluster information regarding each of the plurality of clusters, into which the assigned requests are respectively assigned; and a descriptor suitable for updating a descriptor report such that the cluster information regarding each of the plurality of clusters and the assigned requests correspond to each other, respectively.

Abstract: A memory system includes a memory device including first and second memory blocks, a cache read mode setting unit suitable for determining a memory block to store and manage map data for user data among the first memory block and the second memory block, and a controller suitable for performing a read operation on the user data and the map data and an update operation on the map data in parallel.

Abstract: An operating method of a memory system may include: transmitting, by a descriptor generation unit, cache descriptors to a memory interface unit, and suspending the ordered cache output descriptors by ordering cache output descriptors in a response order; generating, by the memory interface unit, cache commands based on the cache descriptors, and transmitting the cache commands to memory devices; transmitting, by the descriptor generation unit, the cache output descriptors to the memory interface unit according to the response order, when the suspensions of the cache output descriptors are released; and generating, by the memory interface unit, cache output commands based on the cache output descriptors, and transmitting the cache output commands to the memory devices.

Abstract: A memory system includes: a plurality of nonvolatile memory devices each including a plurality of memory blocks; and a controller configured to select an innocent open super block among super blocks formed across the nonvolatile memory devices when determining that sequential write operations are to be performed, and perform the sequential write operations on the innocent open super block.

Abstract: A memory system may include: a controller; and a nonvolatile memory device including memory units, and configured to perform a read operation on the memory units according to control of the controller. The controller may arrange a processing order of the memory units based on an internal read time of each of the memory units, and control the read operation according to the arranged processing order.

Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for programming data to the nonvolatile memory device or reading out data from the nonvolatile memory device, wherein the controller is configured to include a debugging data management circuit suitable for storing, in a first storage space, debugging data obtained by collecting an information at an occurrence time of an error as the error occurs during an operation of the controller and copying the debugging data of the first storage space to a second storage space as a debugging data copy event occurs.

Abstract: A memory system includes a first memory comprising at least one first code region; a second memory comprising at least one second code region; and a control unit configured to perform a first operation by executing a first code loaded to the first code region, and perform a second operation by executing a second code loaded to the second code region. The control unit performs a swap operation on the first code and the second code, based on a swap condition.

Abstract: A data storage device may include: a nonvolatile memory device; and a controller including a register, and suitable for extracting an instruction from an working memory according to a preset sequence so as to control the nonvolatile memory device, analyzing and processing the instruction, and storing a result of the processing, and suitable for storing, when a low-voltage detection event occurs, an address of an instruction that is being performed, to a preset data retention space as return instruction information and then performing a reset operation.

Abstract: A memory system includes a controller configured to store start time stamps of a plurality of tasks, determine a delayed task among the tasks by performing a delay check operation based on an end time stamp of a current task and the start time stamps, and assign a priority to the delayed task.

Abstract: A memory system includes a plurality of nonvolatile memory devices sharing a communication line; and a controller including a buffer and a core, and suitable for controlling the nonvolatile memory devices through the communication line, wherein the core determines a type of a plurality of read requests for the nonvolatile memory devices, and sets a usable size of the buffer depending on the type.

Abstract: A data storage device includes a controller including a descriptor generation unit suitable for generating a descriptor and a memory controller suitable for generating a command based on the descriptor; and a nonvolatile memory device including a cell region, and suitable for reading first data from the cell region and buffering the first data in response to a first read command transmitted from the memory controller and outputting the first data to the controller in response to a first cache output command transmitted from the memory controller. The descriptor generation unit transmits an interrupt descriptor to the memory controller. The memory controller generates an interrupt to the descriptor generation unit based on the interrupt descriptor, and transmits the first cache output command to the nonvolatile memory device according to an instruction of the descriptor generation unit for the interrupt.

Abstract: A data storage device includes a nonvolatile memory device; and a controller including a descriptor generation unit, a memory controller and a buffer unit. The descriptor generation unit: transmits a first read descriptor for first data, to the memory controller, queues a first cache output descriptor for the first data, and transmits the first cache output descriptor to the memory controller by referring to a state of clusters included in the buffer unit. The memory controller transmits a first read command to the nonvolatile memory device based on the first read descriptor, and transmits a first cache output command to the nonvolatile memory device based on the first cache output descriptor.

Abstract: A data storage device includes a nonvolatile memory device including a plurality of planes each of which includes a plurality of memory units; and a controller configured to determine a plane distribution of one or more first planes which include one or more first memory units, determine whether the plane distribution satisfies a predetermined condition, select a memory unit in each of one or more second planes, as a second memory unit, depending on the determination result of the satisfaction of the predetermined condition, and perform a read-access in the first memory units and the second memory units simultaneously.

Abstract: A data processing system includes a host device; and a data storage device suitable for detecting a voltage drop state in the voltage received from the host device, changing a first key received from the host device to a second key when detecting the voltage drop state, generating a cyclical redundancy check (CRC) data based on the second key, and transmitting the generated CRC data to the host device.

Abstract: A data storage device includes a nonvolatile memory device; a power management unit suitable for outputting first and second low voltage detection signals, each low voltage detection signal representing a voltage level of a source voltage equal to or lower than a predetermined reference voltage level; and a processor suitable for computing a detection interval between the first low voltage detection signal and the second low voltage detection signal before the first low voltage detection signal, comparing the computed detection interval and a predetermined threshold detection interval, and determining a subject to manage performing of a recovery operation according to low voltage generation based on a comparison result.