Abstract: A method for operating a data storage device, the method comprising: enqueuing requests for a nonvolatile memory device, received from a host device, in a first queue; determining whether a starvation time of a request which is not enqueued in a second queue and has a relatively low priority, among the requests queued in the first queue is reaching to a predetermined response time; and enqueuing, based on a determination result, any one between the request which has the low priority and a request which is not enqueued in the second queue and has a high priority among the requests queued in the first queue, in the second queues

Abstract: A data storage device includes a nonvolatile memory device; a voltage detector suitable for detecting an operating voltage of the nonvolatile memory device; and a control unit suitable for making a first determination whether the operating voltage is dropped intentionally or unintentionally based on a first reference time and an elapsed time for which the operating voltage decreases from a first reference voltage to a second reference voltage.

Abstract: A storage device may include: a protocol processing unit suitable for communicating with a host based on a predetermined protocol, and transferring a response signal to at least one status request signal that is received from the host; a power management unit suitable for supplying a power source voltage, and outputting a detection signal which represents a low voltage detection status where the power source voltage has a voltage level lower than a predetermined voltage level; and a core unit suitable for blocking a transfer of the response signal by the protocol processing unit in response to the detection signal, and processing at least one task request which is received from the host through the protocol processing unit after the blocking.

Abstract: A data storage device includes a nonvolatile memory device; a randomizing unit configured to randomize data to be stored in the nonvolatile memory device and derandomize data read from the nonvolatile memory device, by using seed values; and a control unit configured to, in the case where return is made from a power failure state to a normal state, detect a page of the nonvolatile memory device in which a power problem has occurred, and randomize data of the page in which the power problem has occurred, by using a seed value that is different from a seed value corresponding to the page in which the power problem has occurred, through the randomizing unit.

Abstract: A data storage device includes a nonvolatile memory device; a power management unit suitable for outputting first and second low voltage detection signals, each low voltage detection signal representing a voltage level of a source voltage equal to or lower than a predetermined reference voltage level; and a processor suitable for computing a detection interval between the first low voltage detection signal and the second low voltage detection signal before the first low voltage detection signal, comparing the computed detection interval and a predetermined threshold detection interval, and determining a subject to manage performing of a recovery operation according to low voltage generation based on a comparison result.

Abstract: A method for operating a data storage device includes determining a first weight based on the sum of data sizes for commands queued in a command queue; determining a second weight by summing weights by types of the commands; and controlling an urgent command selection threshold value for selecting an urgent command existing in the command queue, based on at least one of the first weight and the second weight.

Abstract: A data storage device includes a nonvolatile memory device; a voltage detector suitable for detecting an operating voltage of the nonvolatile memory device; and a control unit suitable for making a first determination whether the operating voltage is dropped intentionally or unintentionally based on a first reference time and an elapsed time for which the operating voltage decreases from a first reference voltage to a second reference voltage.

Abstract: A data storage device includes a storage medium including a plurality of logical units; and a controller suitable for accessing the storage medium by logical unit, the controller comprising: a first processor suitable for aligning tasks corresponding to at least one logical unit among the plurality of logical units, depending on a priority; and a second processor suitable for accessing other logical units among the plurality of logical units, wherein the first processor entrusts a task alignment operation for the other logical units, to the second processor, based on workloads of the first and second processors.

Abstract: Provided herein may be a memory system and a method of operating the memory system. The memory system may include a semiconductor device in which data are stored, and a memory controller for communicating with the semiconductor device, sequentially processing tasks included in a descriptor, detecting an error section by checking the tasks in reverse order when an error occurred in the tasks, and reprocessing the tasks included in the detected error section.

Abstract: A data processing system includes a host device; and a data storage device suitable for detecting a voltage drop state in the voltage received from the host device, changing a first key received from the host device to a second key when detecting the voltage drop state, generating a cyclical redundancy check (CRC) data based on the second key, and transmitting the generated CRC data to the host device.

Abstract: A memory system may include: a memory device including a plurality of pages having a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host, a plurality of memory blocks each including the pages, a plurality of planes each including the memory blocks, and a plurality of memory chips each including the planes; and a controller suitable for searching map data of the read data corresponding to a read command received from the host on a basis of a plurality of segments, triggering memory chips corresponding to the map data searched through the searches of the respective segments, reading data stored in the triggered memory chips, and transferring the read data to the host.

Abstract: A data storage device includes a nonvolatile memory device including a memory block, to which a write operation is interrupted and not completed due to at least one time occurrence of sudden power-off (SPO) of the data storage device, wherein the memory block includes at least one first valid page group including one or more valid pages caused before the interruption and at least one invalid page group having one or more invalid pages caused by the interruption; and a controller suitable for writing at least one physical address-to-logical address (P2L) list for the first valid page group into the invalid page group after power-on of the data storage device following the SPO, and recovering an address mapping table for the memory block based on the P2L list after completion of the write operation to the memory block.

Abstract: A memory system may include: a data storage unit comprising a first memory device through which data are inputted/outputted through a first channel and a second memory device through which data are inputted/outputted through a second channel, wherein each of the first and second memory devices comprises a plurality of blocks each having multi-level cells (MLCs); and a controller suitable for selecting a first target block among the plurality of blocks of a channel which includes a first victim block and selecting a second target block among the plurality of blocks of a channel of which does not include the first victim block, and separating data of the MLCs included in the first victim block on a level basis and copying the separated data into the first and second target blocks, respectively, during a garbage collection operation.

Abstract: A data storage device includes a nonvolatile memory device; a buffer memory for storing temporarily data to be transmitted from the nonvolatile memory device to a host device or data to be transmitted from the host device to the nonvolatile memory device; a memory control unit for performing a control operation for controlling the nonvolatile memory device; and a direct memory access (DMA) unit for performing a data transmission operation associated with the buffer memory, according to control of the memory control unit, wherein the DMA block transmits a first data from the nonvolatile memory device to the buffer memory, and wherein the DMA unit transmits a second data from the nonvolatile memory device to the buffer memory, while the first data stored in the buffer memory is transmitted from the buffer memory to the host device.

Abstract: A data storage device includes a nonvolatile memory device; a randomizing unit configured to randomize data to be stored in the nonvolatile memory device and derandomize data read from the nonvolatile memory device, by using seed values; and a control unit configured to, in the case where return is made from a power failure state to a normal state, detect a page of the nonvolatile memory device in which a power problem has occurred, and randomize data of the page in which the power problem has occurred, by using a seed value that is different from a seed value corresponding to the page in which the power problem has occurred, through the randomizing unit.

Abstract: A data storage device includes a nonvolatile memory device; a buffer memory for storing temporarily data to be transmitted from the nonvolatile memory device to a host device or data to be transmitted from the host device to the nonvolatile memory device; a memory control unit for performing a control operation for controlling the nonvolatile memory device; and a direct memory access (DMA) unit for performing a data transmission operation associated with the buffer memory, according to control of the memory control unit, wherein the DMA block transmits a first data from the nonvolatile memory device to the buffer memory, and wherein the DMA unit transmits a second data from the nonvolatile memory device to the buffer memory, while the first data stored in the buffer memory is transmitted from the buffer memory to the host device.

Abstract: A data storage device includes a nonvolatile memory device including a memory block, to which a write operation is interrupted and not completed due to at least one time occurrence of sudden power-off (SPO) of the data storage device, wherein the memory block includes at least one first valid page group including one or more valid pages caused before the interruption and at least one invalid page group having one or more invalid pages caused by the interruption; and a controller suitable for writing at least one physical address-to-logical address (P2L) list for the first valid page group into the invalid page group after power-on of the data storage device following the SPO, and recovering an address mapping table for the memory block based on the P2L list after completion of the write operation to the memory block.

Abstract: A memory system may include: a data storage unit comprising a first memory device through which data are inputted/outputted through a first channel and a second memory device through which data are inputted/outputted through a second channel, wherein each of the first and second memory devices comprises a plurality of blocks each having multi-level cells (MLCs); and a controller suitable for selecting a first target block among the plurality of blocks of a channel which includes a first victim block and selecting a second target block among the plurality of blocks of a channel of which does not include the first victim block, and separating data of the MLCs included in the first victim block on a level basis and copying the separated data into the first and second target blocks, respectively, during a garbage collection operation.

Abstract: A data storage device includes a plurality of memory apparatuses, a searching unit configured to search for “k” physical addresses mapped to “k” continuous logical addresses, and a processor configured to determine numerical consecutiveness of “i” logical addresses mapped to “i” continuous physical addresses consecutive to an Kth physical address of the “k” physical addresses, and transmit a first pre-read command with respect to a first pre-read memory area corresponding to the “i” continuous physical addresses and first read-estimated physical addresses consecutive to the “i” continuous physical addresses when the numerical consecutiveness is admitted.

Abstract: This technology relates to a memory system supporting a one-shot program and an operating method of the memory system The memory system may include: a first memory device comprising a first multi-level cell and a first multi-level buffer, a second memory device comprising a second multi-level cell and a second multi-level buffer, and a controller suitable for buffering input data in the first and the second multi-level buffers in an interleaving way, for rearranging and storing the buffered input data in a multi-level buffer selected from the first and second multi-level buffers if the input data have a size smaller than or equal to a preset size, wherein a one-shot program is performed on a memory device including the selected multi-level buffer.