Abstract: A memory system may include: a memory device including a plurality of pages having a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host, a plurality of memory blocks each including the pages, a plurality of planes each including the memory blocks, and a plurality of memory chips each including the planes; and a controller suitable for searching map data of the read data corresponding to a read command received from the host on a basis of a plurality of segments, triggering memory chips corresponding to the map data searched through the searches of the respective segments, reading data stored in the triggered memory chips, and transferring the read data to the host.

Abstract: A memory system includes a plurality of memory chips each including memory regions and page buffers; an address table suitable for storing mapping information for mapping physical addresses and logical addresses; a target table suitable for storing sequential physical addresses and sequential logical addresses; a selective output block suitable for selecting the memory regions as pages under selection by units of a page according to a preset order, based on the sequential physical addresses, and outputting data stored in page buffers of memory chips under selection corresponding to the pages under selection; and an expected read block suitable for reading data stored in selection-expected pages, which is to be selected following the pages under selection according to the preset order, to store in page buffers of selection-expected memory chips corresponding to the selection-expected pages, while the data stored in the page buffers under selection are outputted.

Abstract: A data storage device includes a plurality of memory apparatuses, a searching unit configured to search for “k” physical addresses mapped to “k” continuous logical addresses, and a processor configured to determine numerical consecutiveness of “i” logical addresses mapped to “i” continuous physical addresses consecutive to an Kth physical address of the “k” physical addresses, and transmit a first pre-read command with respect to a first pre-read memory area corresponding to the “i” continuous physical addresses and first read-estimated physical addresses consecutive to the “i” continuous physical addresses when the numerical consecutiveness is admitted.

Abstract: A memory system includes a plurality of memory chips each including memory regions and page buffers; an address table suitable for storing mapping information for mapping physical addresses and logical addresses; a target table suitable for storing sequential physical addresses and sequential logical addresses; a selective output block suitable for selecting the memory regions as pages under selection by units of a page according to a preset order, based on the sequential physical addresses, and outputting data stored in page buffers of memory chips under selection corresponding to the pages under selection; and an expected read block suitable for reading data stored in selection-expected pages, which is to be selected following the pages under selection according to the preset order, to store in page buffers of selection-expected memory chips corresponding to the selection-expected pages, while the data stored in the page buffers under selection are outputted.