Patents by Inventor Jeffrey B. Shealy

Jeffrey B. Shealy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200119715
    Abstract: A method of manufacture and structure for an acoustic resonator device having a hybrid piezoelectric stack with a strained single crystal layer and a thermally-treated polycrystalline layer. The method can include forming a strained single crystal piezoelectric layer overlying the nucleation layer and having a strain condition and piezoelectric layer parameters, wherein the strain condition is modulated by nucleation growth parameters and piezoelectric layer parameters to improve one or more piezoelectric properties of the strained single crystal piezoelectric layer. Further, the method can include forming a polycrystalline piezoelectric layer overlying the strained single crystal piezoelectric layer, and performing a thermal treatment on the polycrystalline piezoelectric layer to form a recrystallized polycrystalline piezoelectric layer. The resulting device with this hybrid piezoelectric stack exhibits improved electromechanical coupling and wide bandwidth performance.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 16, 2020
    Inventors: Shawn R. GIBB, Craig MOE, Jeff LEATHERSICH, Steven DENBAARS, Jeffrey B. SHEALY
  • Publication number: 20200112298
    Abstract: An RF circuit device using modified lattice, lattice, and ladder circuit topologies. The devices can include four resonator devices and four shunt resonator devices. In the ladder topology, the resonator devices are connected in series from an input port to an output port while shunt resonator devices are coupled the nodes between the resonator devices. In the lattice topology, a top and a bottom serial configurations each includes a pair of resonator devices that are coupled to differential input and output ports. A pair of shunt resonators is cross-coupled between each pair of a top serial configuration resonator and a bottom serial configuration resonator. The modified lattice topology adds baluns or inductor devices between top and bottom nodes of the top and bottom serial configurations of the lattice configuration. These topologies may be applied using single crystal or polycrystalline bulk acoustic wave (BAW) resonators.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Inventors: Jeffrey B. SHEALY, Rohan W. HOULDEN, David M. AICHELE
  • Patent number: 10615773
    Abstract: A system for a wireless communication infrastructure using single crystal devices. The wireless system can include a controller coupled to a power source, a signal processing module, and a plurality of transceiver modules. Each of the transceiver modules includes a transmit module configured on a transmit path and a receive module configured on a receive path. The transmit modules each include at least a transmit filter having one or more filter devices, while the receive modules each include at least a receive filter. Each of these filter devices includes a single crystal acoustic resonator device with at least a first electrode material, a single crystal material, and a second electrode material. Wireless infrastructures using the present single crystal technology perform better in high power density applications, enable higher out of band rejection (OOBR), and achieve higher linearity as well.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: April 7, 2020
    Assignee: Akoustis, Inc.
    Inventors: Ramakrishna Vetury, Shawn R. Gibb, Mark D. Boomgarden, Jeffrey B. Shealy
  • Publication number: 20200091406
    Abstract: A method of manufacturing an integrated circuit. This method includes forming an epitaxial material comprising single crystal piezo material overlying a surface region of a substrate to a desired thickness and forming a trench region to form an exposed portion of the surface region through a pattern provided in the epitaxial material. Also, the method includes forming a topside landing pad metal and a first electrode member overlying a portion of the epitaxial material and a second electrode member overlying the topside landing pad metal. Furthermore, the method can include processing the backside of the substrate to form a backside trench region exposing a backside of the epitaxial material and the landing pad metal and forming a backside resonator metal material overlying the backside of the epitaxial material to couple to the second electrode member overlying the topside landing pad metal.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 19, 2020
    Inventor: Jeffrey B. SHEALY
  • Patent number: 10581398
    Abstract: A method of manufacture for an acoustic resonator device. The method includes forming a nucleation layer characterized by nucleation growth parameters overlying a substrate and forming a strained piezoelectric layer overlying the nucleation layer. The strained piezoelectric layer is characterized by a strain condition and piezoelectric layer parameters. The process of forming the strained piezoelectric layer can include an epitaxial growth process configured by nucleation growth parameters and piezoelectric layer parameters to modulate the strain condition in the strained piezoelectric layer. By modulating the strain condition, the piezoelectric properties of the resulting piezoelectric layer can be adjusted and improved for specific applications.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: March 3, 2020
    Assignee: Akoustis, Inc.
    Inventors: Shawn R. Gibb, Alexander Y. Feldman, Mark D. Boomgarden, Michael P. Lewis, Ramakrishna Vetury, Jeffrey B. Shealy
  • Publication number: 20200067486
    Abstract: An acoustic resonator device and method thereof. The device includes a substrate member having an air cavity region. A piezoelectric layer is coupled to and configured overlying the substrate member and the air cavity region. The piezoelectric layer is configured to be characterized by an x-ray rocking curve Full Width at Half Maximum (FWHM) ranging from 0 degrees to 2 degrees. A top electrode is coupled to and configured overlying the piezoelectric layer, while a bottom electrode coupled to and configured underlying the piezoelectric layer within the air cavity region. The configuration of the materials of the piezoelectric layer and the substrate member to achieve the specific FWHM range improves a power handling capability characteristic and a power durability characteristic.
    Type: Application
    Filed: August 27, 2019
    Publication date: February 27, 2020
    Inventors: Jeffrey B. SHEALY, Shawn R. GIBB, Rohan W. HOULDEN, Joel M. MORGAN
  • Publication number: 20200013948
    Abstract: A method of forming a piezoelectric thin film can be provided by heating a substrate in a process chamber to a temperature between about 350 degrees Centigrade and about 850 degrees Centigrade to provide a sputtering temperature of the substrate and sputtering a Group III element from a target in the process chamber onto the substrate at the sputtering temperature to provide the piezoelectric thin film including a nitride of the Group III element on the substrate to have a crystallinity of less than about 1.0 degree at Full Width Half Maximum (FWHM) to about 10 arcseconds at FWHM measured using X-ray diffraction (XRD).
    Type: Application
    Filed: July 16, 2019
    Publication date: January 9, 2020
    Inventors: Craig Moe, Jeffrey B. Shealy, Mary Winters
  • Patent number: 10523180
    Abstract: A method of manufacture and structure for an acoustic resonator device having a hybrid piezoelectric stack with a strained single crystal layer and a thermally-treated polycrystalline layer. The method can include forming a strained single crystal piezoelectric layer overlying the nucleation layer and having a strain condition and piezoelectric layer parameters, wherein the strain condition is modulated by nucleation growth parameters and piezoelectric layer parameters to improve one or more piezoelectric properties of the strained single crystal piezoelectric layer. Further, the method can include forming a polycrystalline piezoelectric layer overlying the strained single crystal piezoelectric layer, and performing a thermal treatment on the polycrystalline piezoelectric layer to form a recrystallized polycrystalline piezoelectric layer. The resulting device with this hybrid piezoelectric stack exhibits improved electromechanical coupling and wide bandwidth performance.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 31, 2019
    Assignee: Akoustis, Inc.
    Inventors: Shawn R. Gibb, Craig Moe, Jeff Leathersich, Steven Denbaars, Jeffrey B. Shealy
  • Patent number: 10516377
    Abstract: A method of manufacturing an integrated circuit. This method includes forming an epitaxial material comprising single crystal piezo material overlying a surface region of a substrate to a desired thickness and forming a trench region to form an exposed portion of the surface region through a pattern provided in the epitaxial material. Also, the method includes forming a topside landing pad metal and a first electrode member overlying a portion of the epitaxial material and a second electrode member overlying the topside landing pad metal. Furthermore, the method can include processing the backside of the substrate to form a backside trench region exposing a backside of the epitaxial material and the landing pad metal and forming a backside resonator metal material overlying the backside of the epitaxial material to couple to the second electrode member overlying the topside landing pad metal.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: December 24, 2019
    Assignee: Akoustis, Inc.
    Inventor: Jeffrey B. Shealy
  • Publication number: 20190385893
    Abstract: A method of wafer scale packaging acoustic resonator devices and an apparatus therefor. The method including providing a partially completed semiconductor substrate comprising a plurality of single crystal acoustic resonator devices, each having a first electrode member, a second electrode member, and an overlying passivation material. At least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, an under metal material overlying the repassivation material. Copper pillar interconnect structures are then configured overlying the electrode members, and solder bump structures are form overlying the copper pillar interconnect structures.
    Type: Application
    Filed: August 21, 2019
    Publication date: December 19, 2019
    Inventor: Jeffrey B. SHEALY
  • Publication number: 20190372549
    Abstract: An RF circuit device using modified lattice, lattice, and ladder circuit topologies. The devices can include four resonator devices and four shunt resonator devices. In the ladder topology, the resonator devices are connected in series from an input port to an output port while shunt resonator devices are coupled the nodes between the resonator devices. In the lattice topology, a top and a bottom serial configurations each includes a pair of resonator devices that are coupled to differential input and output ports. A pair of shunt resonators is cross-coupled between each pair of a top serial configuration resonator and a bottom serial configuration resonator. The modified lattice topology adds baluns or inductor devices between top and bottom nodes of the top and bottom serial configurations of the lattice configuration. These topologies may be applied using single crystal or polycrystalline bulk acoustic wave (BAW) resonators.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Inventors: Rohan W. HOULDEN, Ya SHEN, David M. AICHELE, Jeffrey B. SHEALY
  • Publication number: 20190371792
    Abstract: A method of manufacture and structure for a monolithic single chip single crystal device. The method can include forming a first single crystal epitaxial layer overlying the substrate and forming one or more second single crystal epitaxial layers overlying the first single crystal epitaxial layer. The first single crystal epitaxial layer and the one or more second single crystal epitaxial layers can be processed to form one or more active or passive device components. Through this process, the resulting device includes a monolithic epitaxial stack integrating multiple circuit functions.
    Type: Application
    Filed: August 5, 2019
    Publication date: December 5, 2019
    Applicant: Akoustis, Inc.
    Inventors: Shawn R. GIBB, David M. AICHELE, Ramakrishna VETURY, Mark D. BOOMGARDEN, Jeffrey B. SHEALY
  • Publication number: 20190372555
    Abstract: In an array of single crystal acoustic resonators, the effective coupling coefficient of first and second strained single crystal filters are individually tailored in order to achieve desired frequency responses. In a duplexer embodiment, the effective coupling coefficient of a transmit band-pass filter is lower than the effective coupling coefficient of a receive band-pass filter of the same duplexer. The coefficients can be tailored by varying the ratio of the thickness of a piezoelectric layer to the total thickness of electrode layers or by forming a capacitor in parallel with an acoustic resonator within the filter for which the effective coupling coefficient is to be degraded. Further, a strained piezoelectric layer can be formed overlying a nucleation layer characterized by nucleation growth parameters, which can be configured to modulate a strain condition in the strained piezoelectric layer to adjust piezoelectric properties for improved performance in specific applications.
    Type: Application
    Filed: June 1, 2018
    Publication date: December 5, 2019
    Inventors: Jeffrey B. SHEALY, Shawn R. GIBB
  • Publication number: 20190341906
    Abstract: An RF circuit device using modified lattice, lattice, and ladder circuit topologies. The devices can include four resonator devices and four shunt resonator devices. In the ladder topology, the resonator devices are connected in series from an input port to an output port while shunt resonator devices are coupled the nodes between the resonator devices. In the lattice topology, a top and a bottom serial configurations each includes a pair of resonator devices that are coupled to differential input and output ports. A pair of shunt resonators is cross-coupled between each pair of a top serial configuration resonator and a bottom serial configuration resonator. The modified lattice topology adds baluns or inductor devices between top and bottom nodes of the top and bottom serial configurations of the lattice configuration. These topologies may be applied using single crystal or polycrystalline bulk acoustic wave (BAW) resonators.
    Type: Application
    Filed: July 17, 2019
    Publication date: November 7, 2019
    Inventors: Rohan W. HOULDEN, David M. AICHELE, Jeffrey B. SHEALY
  • Publication number: 20190326885
    Abstract: An RF circuit device using modified lattice, lattice, and ladder circuit topologies. The devices can include four resonator devices and four shunt resonator devices. In the ladder topology, the resonator devices are connected in series from an input port to an output port while shunt resonator devices are coupled the nodes between the resonator devices. In the lattice topology, a top and a bottom serial configurations each includes a pair of resonator devices that are coupled to differential input and output ports. A pair of shunt resonators is cross-coupled between each pair of a top serial configuration resonator and a bottom serial configuration resonator. The modified lattice topology adds baluns or inductor devices between top and bottom nodes of the top and bottom serial configurations of the lattice configuration. These topologies may be applied using single crystal or polycrystalline bulk acoustic wave (BAW) resonators.
    Type: Application
    Filed: July 5, 2019
    Publication date: October 24, 2019
    Inventors: Rohan W. HOULDEN, Jeffrey B. SHEALY, Shawn R. GIBB, David M. AICHELE
  • Publication number: 20190312027
    Abstract: A method of manufacture and structure for a monolithic single chip single crystal device. The method can include forming a first single crystal epitaxial layer overlying the substrate and forming one or more second single crystal epitaxial layers overlying the first single crystal epitaxial layer. The first single crystal epitaxial layer and the one or more second single crystal epitaxial layers can be processed to form one or more active or passive device components. Through this process, the resulting device includes a monolithic epitaxial stack integrating multiple circuit functions.
    Type: Application
    Filed: January 12, 2017
    Publication date: October 10, 2019
    Inventors: Shawn R. GIBB, David AICHELE, Ramakrishna VETURY, Mark D. BOOMGARDEN, Jeffrey B. SHEALY
  • Publication number: 20190305753
    Abstract: A method and structure for an essentially single crystal acoustic electronic device. The device includes a substrate having an enhancement layer formed overlying its surface region and an air cavity formed through a portion of the substrate. An essentially single crystal piezoelectric material is formed overlying the air cavity and a portion of the enhancement layer. Also, a first electrode material coupled to the backside surface region of the crystal piezoelectric material and spatially configured within the cavity. A second electrode material is formed overlying the topside of the piezoelectric material, and a dielectric layer formed overlying the second electrode material. Further, one or more shunt layers can be formed around the perimeter of a resonator region of the device to connect the piezoelectric material to the enhancement layer.
    Type: Application
    Filed: June 20, 2019
    Publication date: October 3, 2019
    Inventor: Jeffrey B. SHEALY
  • Patent number: 10431580
    Abstract: A method of manufacture and structure for a monolithic single chip single crystal device. The method can include forming a first single crystal epitaxial layer overlying the substrate and forming one or more second single crystal epitaxial layers overlying the first single crystal epitaxial layer. The first single crystal epitaxial layer and the one or more second single crystal epitaxial layers can be processed to form one or more active or passive device components. Through this process, the resulting device includes a monolithic epitaxial stack integrating multiple circuit functions.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: October 1, 2019
    Assignee: Akoustis, Inc.
    Inventors: Shawn R. Gibb, David Aichele, Ramakrishna Vetury, Mark D. Boomgarden, Jeffrey B. Shealy
  • Patent number: 10431490
    Abstract: A method of wafer scale packaging acoustic resonator devices and an apparatus therefor. The method including providing a partially completed semiconductor substrate comprising a plurality of single crystal acoustic resonator devices, each having a first electrode member, a second electrode member, and an overlying passivation material. At least one of the devices to be configured with an external connection, a repassivation material overlying the passivation material, an under metal material overlying the repassivation material. Copper pillar interconnect structures are then configured overlying the electrode members, and solder bump structures are form overlying the copper pillar interconnect structures.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 1, 2019
    Assignee: Akoustis, Inc.
    Inventor: Jeffrey B. Shealy
  • Publication number: 20190288658
    Abstract: A method and structure for a transfer process for an acoustic resonator device. In an example, a bulk acoustic wave resonator (BAWR) with an air reflection cavity is formed. A piezoelectric thin film is grown on a crystalline substrate. A first patterned electrode is deposited on the surface of the piezoelectric film. An etched sacrificial layer is deposited over the first electrode and a planarized support layer is deposited over the sacrificial layer, which is then bonded to a substrate wafer. The crystalline substrate is removed and a second patterned electrode is deposited over a second surface of the film. The sacrificial layer is etched to release the air reflection cavity. Also, a cavity can instead be etched into the support layer prior to bonding with the substrate wafer. Alternatively, a reflector structure can be deposited on the first electrode, replacing the cavity.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Inventors: Dae Ho KIM, Mary WINTERS, Ramakrishna VETURY, Jeffrey B. SHEALY