Patents by Inventor Jeffrey Babcock

Jeffrey Babcock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150270335
    Abstract: Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 24, 2015
    Inventors: Alexei Sadovnikov, Jeffrey A. Babcock
  • Patent number: 8728920
    Abstract: A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: May 20, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Zia Alan Shafi, Jeffrey A. Babcock
  • Patent number: 8703568
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: April 22, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Patent number: 8669157
    Abstract: The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: March 11, 2014
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Patent number: 8648391
    Abstract: The product of the breakdown voltage (BVCEO) and the cutoff frequency (fT) of a SiGe heterojunction bipolar transistor (HBT) is increased beyond the Johnson limit by utilizing a doped region with a hollow core that extends down from the base to the heavily-doped buried collector region. The doped region and the buried collector region have opposite dopant types.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: February 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Publication number: 20130248935
    Abstract: A pnp SiGe heterojunction bipolar transistor (HBT) reduces the rate that p-type dopant atoms in the p+ emitter of the transistor out diffuse into a lowly-doped region of the base of the transistor by epitaxially growing the emitter to include a single-crystal germanium region and an overlying single-crystal silicon region.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 26, 2013
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Publication number: 20130249057
    Abstract: The product of the breakdown voltage (BVCEO) and the cutoff frequency (fT) of a SiGe heterojunction bipolar transistor (HBT) is increased beyond the Johnson limit by utilizing a doped region with a hollow core that extends down from the base to the heavily-doped buried collector region. The doped region and the buried collector region have opposite dopant types.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 26, 2013
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Patent number: 8525233
    Abstract: A pnp SiGe heterojunction bipolar transistor (HBT) reduces the rate that p-type dopant atoms in the p+ emitter of the transistor out diffuse into a lowly-doped region of the base of the transistor by epitaxially growing the emitter to include a single-crystal germanium region and an overlying single-crystal silicon region.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: September 3, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Patent number: 8453494
    Abstract: A semiconductor-based gas detector enhances the collection of gas molecules and also provides a self-contained means for removing collected gas molecules by utilizing one or more electric fields to transport the gas molecules to and away from a metallic material that has a high permeability to the gas molecules.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: June 4, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey A. Babcock, Peter J. Hopper, Yuri Mirgorodski
  • Patent number: 8455980
    Abstract: The self heating of a high-performance bipolar transistor that is formed on a fully-isolated single-crystal silicon region of a silicon-on-insulator (SOI) structure is substantially reduced by forming a Schottky structure in the same fully-isolated single-crystal silicon region as the bipolar transistor is formed.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: June 4, 2013
    Assignee: National Semiconductor Corporation
    Inventor: Jeffrey A. Babcock
  • Publication number: 20130009271
    Abstract: The self heating of a high-performance bipolar transistor that is formed on a fully-isolated single-crystal silicon region of a silicon-on-insulator (SOI) structure is substantially reduced by forming a Schottky structure in the same fully-isolated single-crystal silicon region as the bipolar transistor is formed.
    Type: Application
    Filed: July 8, 2011
    Publication date: January 10, 2013
    Inventor: Jeffrey A. Babcock
  • Patent number: 8299578
    Abstract: In a SOI process, a high voltage BJT structure with BVCEO versus FT control is provided by including a bias shield over the laterally extending collector region and controlling the bias of the shield.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: October 30, 2012
    Assignee: National Semiconductor Corporation
    Inventor: Jeffrey Babcock
  • Publication number: 20120244689
    Abstract: A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode.
    Type: Application
    Filed: June 1, 2012
    Publication date: September 27, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Zia Alan Shafi, Jeffrey A. Babcock
  • Publication number: 20120230118
    Abstract: The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
    Type: Application
    Filed: May 21, 2012
    Publication date: September 13, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Patent number: 8247300
    Abstract: An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26?). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26?), to inhibit the diffusion of dopant from the buried collector region (26?) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26?) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26?) can diffuse upward to meet the contact (33).
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 21, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Manfred Schiekofer, Scott G. Balster, Gregory E. Howard, Alfred Hausler
  • Publication number: 20120164802
    Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
    Type: Application
    Filed: January 26, 2012
    Publication date: June 28, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Angelo Pinto, Scott Balster, Alfred Haeusler, Gregory E. Howard
  • Patent number: 8207559
    Abstract: In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N? type or P? type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N? and P? channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET).
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: June 26, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Natalia Lavrovskaya, Saurabh Desai, Alexei Sadovnikov, Zia Alan Shafi
  • Patent number: 8193602
    Abstract: A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: June 5, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Zia Alan Shafi, Jeffrey A. Babcock
  • Patent number: 8183621
    Abstract: The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: May 22, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Publication number: 20120060587
    Abstract: A semiconductor-based gas detector enhances the collection of gas molecules and also provides a self-contained means for removing collected gas molecules by utilizing one or more electric fields to transport the gas molecules to and away from a metallic material that has a high permeability to the gas molecules.
    Type: Application
    Filed: September 13, 2010
    Publication date: March 15, 2012
    Inventors: Jeffrey A. Babcock, Peter J. Hopper, Yuri Mirgorodski