Abstract: A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. At least part of the active region is removed to form a shallow trench opening. A dielectric layer is formed proximate the active region at least partially within the shallow trench opening. At least part of the dielectric layer is removed to form a collector contact region. A collector contact may be formed at the collector contact region. The collector contact may be operable to electrically contact the buried layer.

Abstract: High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.

Abstract: A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region (110) are formed proximate an outer surface of a semiconductor layer (108). An epitaxial layer (111) is deposited outwardly from the trench isolation structure (112). A first insulator layer (116) and a second insulator layer (118) are grown proximate to the epitaxial layer (111). A gate stack (123) that includes portions of the first insulator layer (116 and the second insulator layer (118) is formed outwardly from the epitaxial layer (111). The gate stack (123) also includes a gate (122) with a narrow region (130) and a wide region (132) formed proximate the second insulator layer (118. The epitaxial layer (111) is heated to a temperature sufficient to allow for the epitaxial layer (111) to form a source/drain implant region (126) in the active region (110).

Abstract: A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region (110) are formed proximate an outer surface of a semiconductor layer (108). An epitaxial layer (111) is deposited outwardly from the trench isolation structure (112). A first insulator layer (116) and a second insulator layer (118) are grown proximate to the epitaxial layer (111). A gate stack (123) that includes portions of the first insulator layer (116 and the second insulator layer (118) is formed outwardly from the epitaxial layer (111). The gate stack (123) also includes a gate (122) with a narrow region (130) and a wide region (132) formed proximate the second insulator layer (118. The epitaxial layer (111) is heated to a temperature sufficient to allow for the epitaxial layer (111) to form a source/drain implant region (126) in the active region (110).

Abstract: A transit time device (15, 15′) in a silicon-on-insulator (SOI) technology is disclosed. An anode region (18) and a cathode region (20) are formed on opposing ends of an epitaxial layer (14), with an intrinsic or lightly-doped region (22) disposed therebetween. Sinker structures (30p, 30n) are formed in an overlying epitaxial layer (24) over and in contact with the anode and cathode regions (18, 20). A charge injection terminal may be formed in a sinker structure (32n) in the overlying epitaxial layer (24), if the transit time device (15′) is of the three-terminal type. The device (15, 15′) has extremely low parasitic capacitance to substrate, because of the buried oxide layer (12) underlying the intrinsic region (22).

Abstract: The present invention is directed to a structure and method of forming an integrated circuit MIM capacitor having a relatively capacitance without the need for an additional mask step. Methods of forming integrated circuit capacitors include the steps of forming a standard via and one or more enlarged vias in an electrically insulating layer during the same patterning process and then forming an electrically conductive first electrode layer which fills the standard via and overlays the enlarged vias in a conformal manner. A dielectric layer is then formed over the electrically conductive first electrode layer. Next, an electrically conductive second electrode layer is formed over the dielectric layer, which overlays and/or fills the enlarged vias. A step is then performed to planarize the second electrode layer, the dielectric layer, and the first electrode layer to define the electrodes of a capacitor.

Abstract: A heterojunction bipolar transistor (30) in a silicon-on-insulator (SOI) structure is disclosed. The transistor collector (28), heterojunction base region (20), and intrinsic emitter region (25) are formed in the thin film silicon layer (6) overlying the buried insulator layer (4). A base electrode (10) is formed of polysilicon, and has a polysilicon filament (10f) that extends over the edge of an insulator layer (8) to contact the silicon layer (6). After formation of insulator filaments (12) along the edges of the base electrode (10) and insulator layer (8), the thin film silicon layer (6) is etched through, exposing an edge. An angled ion implantation then implants the heterojunction species, for example germanium and carbon, into the exposed edge of the thin film silicon layer (6), which after anneal forms the heterojunction base region (20).

Abstract: A method for manufacturing a semiconductor assembly includes forming an active region of a semiconductor substrate and removing at least part of the active region to form a shallow trench opening. The method also includes forming a dielectric layer proximate the active region at least partially within the shallow trench opening and removing at least part of the dielectric layer to form a first device region. The method may include forming a first semiconductor device at the first device region. The first semiconductor device may be operable to facilitate the flow of electric current through the assembly The method may also include forming a second semiconductor device at a second device region, wherein a depth of an area of the active region below the second device region is greater than a depth of an area of the active region below the first device region.

Abstract: An integrated circuit and a method of fabricating the same are disclosed. Complementary bipolar transistors (20p, 20n) are fabricated as vertical bipolar transistors. The emitter polysilicon (35), which is in contact with the underlying single-crystal base material, is doped with a dopant for the appropriate device conductivity type, and also with a diffusion retardant, such as elemental carbon, SiGeC, nitrogen, and the like. The diffusion retardant prevents the dopant from diffusing too fast from the emitter polysilicon (35). Device matching and balance is facilitated, especially for complementary technologies.

Abstract: An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33).

Abstract: A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. At least part of the active region is removed to form a shallow trench opening. A dielectric layer is formed proximate the active region at least partially within the shallow trench opening. At least part of the dielectric layer is removed to form a collector contact region. A collector contact may be formed at the collector contact region. The collector contact may be operable to electrically contact the buried layer.

Abstract: A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure.

Abstract: The present invention is directed to a structure and method of forming an integrated circuit MIM capacitor having a relatively capacitance without the need for an additional mask step. Methods of forming integrated circuit capacitors include the steps of forming a standard via and one or more enlarged vias in an electrically insulating layer during the same patterning process and then forming an electrically conductive first electrode layer which fills the standard via and overlays the enlarged vias in a conformal manner. A dielectric layer is then formed over the electrically conductive first electrode layer. Next, an electrically conductive second electrode layer is formed over the dielectric layer, which overlays and/or fills the enlarged vias. A step is then performed to planarize the second electrode layer, the dielectric layer, and the first electrode layer to define the electrodes of a capacitor.

Abstract: High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.

Abstract: A voltage controlled capacitor sandwiched between a buried oxide and a shallow trench insulator to form a near ideal P+ to n-well diode with minimal parasitic capacitance and resistance.

Abstract: A transit time device (15, 15′) in a silicon-on-insulator (SOI) technology is disclosed. An anode region (18) and a cathode region (20) are formed on opposing ends of an epitaxial layer (14), with an intrinsic or lightly-doped region (22) disposed therebetween. Sinker structures (30p, 30n) are formed in an overlying epitaxial layer (24) over and in contact with the anode and cathode regions (18, 20). A charge injection terminal may be formed in a sinker structure (32n) in the overlying epitaxial layer (24), if the transit time device (15′) is of the three-terminal type. The device (15, 15′) has extremely low parasitic capacitance to substrate, because of the buried oxide layer (12) underlying the intrinsic region (22).

Abstract: A semiconductor device (100) and a method for constructing a semiconductor device (100) are disclosed. A trench isolation structure (112) and an active region (110) are formed proximate an outer surface of a semiconductor layer (108). An epitaxial layer (111) is deposited outwardly from the trench isolation structure (112). A first insulator layer (116) and a second insulator layer (118) are grown proximate to the epitaxial layer (111). A gate stack (123) that includes portions of the first insulator layer (116 and the second insulator layer (118) is formed outwardly from the epitaxial layer (111). The gate stack (123) also includes a gate (122) with a narrow region (130) and a wide region (132) formed proximate the second insulator layer (118. The epitaxial layer (111) is heated to a temperature sufficient to allow for the epitaxial layer (111) to form a source/drain implant region (126) in the active region (110).

Abstract: The instant invention describes a programmable neuron MOSFET structure formed on SOI substrates. A number of input capacitor structures (241, 231) are formed on a SOI substrate. The substrate region of the capacitors (330, 340) are completely isolated from each other by isolation structures (270). In addition the transistor structure (210) of the neuron MOSFET is completely isolated from the capacitor structures (241, 231) by the isolation structure (270). The neuron MOSFET also comprises a contiguous floating conductive layer (200, 230, and 240) which forms the gate structure of the capacitors (230, 240) and the floating gate (200) of the transistor structure.

Abstract: The present invention is directed to a structure and method of forming an integrated circuit MIM capacitor having a relatively capacitance without the need for an additional mask step. Methods of forming integrated circuit capacitors include the steps of forming a standard via and one or more enlarged vias in an electrically insulating layer during the same patterning process and then forming an electrically conductive first electrode layer which fills the standard via and overlays the enlarged vias in a conformal manner. A dielectric layer is then formed over the electrically conductive first electrode layer. Next, an electrically conductive second electrode layer is formed over the dielectric layer, which overlays and/or fills the enlarged vias. A step is then performed to planarize the second electrode layer, the dielectric layer, and the first electrode layer to define the electrodes of a capacitor.

Abstract: The instant invention describes a programmable neuron MOSFET structure formed on SOI substrates. A number of input capacitor structures (241, 231) are formed on a SOI substrate. The substrate region of the capacitors (330, 340) are completely isolated from each other by isolation structures (270). In addition the transistor structure (210) of the neuron MOSFET is completely isolated from the capacitor structures (241, 231) by the isolation structure (270). The neuron MOSFET also comprises a contiguous floating conductive layer (200, 230, and 240) which forms the gate structure of the capacitors (230, 240) and the floating gate (200) of the transistor structure.