Abstract: A method includes depositing a first metal layer on a native SiO2 layer that is disposed on at least one of a source and a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET). A metal oxide layer is formed from the native SiO2 layer and the first metal layer, wherein the remaining first metal layer, the metal oxide layer, and the at least one of the source and the drain form a metal-insulator-semiconductor (MIS) contact.

Abstract: A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a p-type MOS (PMOS) device by chemical vapor deposition (CVD) or non-energetic physical vapor deposition (PVD). The method further includes selectively performing a rapid thermal anneal (RTA) process on the first metal layer after forming the first metal layer.

Abstract: A semiconductor fin is on a substrate, and extends in a longitudinal direction parallel to the substrate. The fin projects, in a vertical direction, to a fin top at a fin height above the substrate. An embedded fin stressor element is embedded in the fin. The fin stressor element is configured to urge a vertical compression force within the fin, parallel to the vertical direction. Optionally, the semiconductor material includes silicon, and embedded fin stressor element includes silicon dioxide.

Abstract: A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer.

Abstract: A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The germanium-doped layer has a higher germanium concentration than the inner region. The FinFET further includes a gate dielectric over the germanium-doped layer, a gate electrode over the gate dielectric, a source region connected to a first end of the semiconductor fin, and a drain region connected to a second end of the semiconductor fin opposite the first end. Through the doping of germanium in the semiconductor fin, the threshold voltage may be tuned.

Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

Abstract: A particular semiconductor device includes a substrate, a source contact, a drain contact, and a metal-gate. The substrate includes a source region, a drain region, and a channel. The source contact is coupled to the source region. The drain contact is coupled to the drain region. The metal-gate is coupled to the channel. The metal-gate includes an amorphous metal layer.

Abstract: Tie-off structures for middle-of-line (MOL) manufactured integrated circuits, and related methods are disclosed. As a non-limiting example, the tie-off structure may be used to tie-off a drain or source of a transistor to the gate of the transistor, such as provided in a dummy gate used for isolation purposes. In this regard in one aspect, a MOL stack is provided that includes a metal gate connection that is coupled to a metal layer through metal structure disposed in and above a dielectric layer above a gate associated with the metal gate connection. By coupling the metal gate connection to the metal layer, the gate of a transistor may be coupled or “tied-off” to a source or drain element of the transistor. This may avoid the need to etch the metal gate connection provided below the dielectric layer to provide sufficient connectivity between the metal layer and the metal gate connection.

Abstract: Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via are disclosed. Related methods are also disclosed. In particular, different metal lines in a metal layer may need to be electrically interconnected during a MOL process for an IC. In this regard, to allow for metal lines to be interconnected without providing such interconnections above the metal lines that may be difficult to provide in a printing process for example, in an exemplary aspect, an elongated or expanded via(s) is provided in a MOL layer in an IC. The elongated via is provided in the MOL layer below the metal layer in the MOL layer and extended across two or more adjacent metal layers in the metal layer of the MOL layer. Moving the interconnections above the MOL layer can simplify the manufacturing of ICs, particularly at low nanometer (nm) node sizes.

Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.

Abstract: A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.

Abstract: A device includes a first structure and a second structure. The second structure is separated from the first structure by a cavity. The device further includes a seal material, an etch stop material defining an etched region, and a self-aligned contact (SAC). The seal material is configured to seal the cavity, and the SAC is formed within the etched region. The SAC adjoins the seal material, the etch stop material, or a combination thereof.

Abstract: A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film.

Abstract: A fin field-effect transistor (FinFET) includes a gate stack on a surface of a semiconductor fin. The semiconductor fin may include a capping material and a stressor material. The stressor material is confined by the capping material to a region proximate the gate stack. The stressor material provides stress on the semiconductor fin proximate the gate stack.

Abstract: An apparatus includes a first interconnect and a first barrier structure. The first barrier structure is in contact with a dielectric material. The apparatus further includes a first protective structure in contact with the first barrier structure and an etch stop layer. An airgap is defined at least in part by the first protective structure and the etch stop layer.

Abstract: An apparatus includes a metal gate, a substrate material, and an oxide layer between the metal gate and the substrate material. The oxide layer includes a hafnium oxide layer contacting the metal gate and a silicon dioxide layer contacting the substrate material and contacting the hafnium oxide layer. The metal gate, the substrate material, and the oxide layer are included in a one-time programmable (OTP) memory device. The OTP memory device includes a transistor. A non-volatile state of the OTP memory device is based on a threshold voltage shift of the OTP memory device.

Abstract: A method includes depositing a first metal layer on a native SiO2 layer that is disposed on at least one of a source and a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET). A metal oxide layer is formed from the native SiO2 layer and the first metal layer, wherein the remaining first metal layer, the metal oxide layer, and the at least one of the source and the drain form a metal-insulator-semiconductor (MIS) contact.

Abstract: Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines, the air gaps to reduce capacitance. An interposer is coupled to the integrated circuit, to reduce stress on the two or more Tungsten lines and the at least one air gap. A laminated package substrate may be attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.

Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.

Abstract: A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.