Patents by Inventor Jeffrey Junhao Xu
Jeffrey Junhao Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9196583Abstract: Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material.Type: GrantFiled: May 9, 2014Date of Patent: November 24, 2015Assignee: QUALCOMM INCORPORATEDInventors: John Jianhong Zhu, Jeffrey Junhao Xu, Stanley Seungchul Song, Kern Rim, Zhongze Wang
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Publication number: 20150325515Abstract: Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material.Type: ApplicationFiled: May 9, 2014Publication date: November 12, 2015Applicant: QUALCOMM IncorporatedInventors: John Jianhong ZHU, Jeffrey Junhao XU, Stanley Seungchul SONG, Kern RIM, Zhongze WANG
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Patent number: 9165929Abstract: A complementary fin field-effect transistor (FinFET) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a semiconductor substrate. The first material may have a compressive strain. The FinFET device also includes an n-type device having an re-channel fin. The n-channel fin may include a second material having a tensile strain that is lattice mismatched relative to the semiconductor substrate. The p-type device and the n-type device cooperate to form the complementary FinFET device.Type: GrantFiled: July 2, 2014Date of Patent: October 20, 2015Assignee: QUALCOMM INCORPORATEDInventors: Kern Rim, Jeffrey Junhao Xu, Stanley Seungchul Song
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Publication number: 20150270134Abstract: A method includes forming a first metal layer on source/drain regions of an n-type metal-oxide-semiconductor (NMOS) device and on source/drain regions of a p-type MOS (PMOS) device by chemical vapor deposition (CVD) or non-energetic physical vapor deposition (PVD). The method further includes selectively performing a rapid thermal anneal (RTA) process on the first metal layer after forming the first metal layer.Type: ApplicationFiled: May 22, 2014Publication date: September 24, 2015Applicant: QUALCOMM IncorporatedInventors: Jeffrey Junhao Xu, Kern Rim, John Jianhong Zhu, Stanley Seungchul Song, Choh Fei Yeap
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Publication number: 20150262875Abstract: A method includes forming an electronic device structure including a substrate, an oxide layer, and a first low-k layer. The method also includes forming openings by patterning the oxide layer, filling the openings with a conductive material to form conductive structures within the openings, and removing the oxide layer using the first low-k layer as an etch stop layer. The conductive structures contact the first low-k layer. Removing the oxide layer includes performing a chemical vapor etch process with respect to the oxide layer to form an etch byproduct and removing the etch byproduct. The method includes forming a second low-k layer using a deposition process that causes the second low-k layer to define one or more cavities. Each cavity is defined between a first conductive structure and an adjacent conductive structure, the first and second conductive structures have a spacing therebetween that is smaller than a threshold distance.Type: ApplicationFiled: August 28, 2014Publication date: September 17, 2015Inventors: Jeffrey Junhao Xu, John Jianhong Zhu, Stanley Seungchul Song, Kern Rim, Choh Fei Yeap
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Publication number: 20150255571Abstract: In a particular embodiment, a method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.Type: ApplicationFiled: July 25, 2014Publication date: September 10, 2015Inventors: Jeffrey Junhao Xu, Kern Rim, John Jianhong Zhu, Stanley Seungchul Song, Mustafa Badaroglu, Vladimir Machkaoutsan, Da Yang, Choh Fei Yeap
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Publication number: 20150249155Abstract: A semiconductor fin is on a substrate, and extends in a longitudinal direction parallel to the substrate. The fin projects, in a vertical direction, to a fin top at a fin height above the substrate. An embedded fin stressor element is embedded in the fin. The fin stressor element is configured to urge a vertical compression force within the fin, parallel to the vertical direction. Optionally, the semiconductor material includes silicon, and embedded fin stressor element includes silicon dioxide.Type: ApplicationFiled: May 19, 2014Publication date: September 3, 2015Applicant: QUALCOMM IncorporatedInventors: Jeffrey Junhao XU, Choh Fei YEAP
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Publication number: 20150249038Abstract: A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.Type: ApplicationFiled: May 9, 2014Publication date: September 3, 2015Applicant: QUALCOMM IncorporatedInventors: Jeffrey Junhao XU, John Jianhong ZHU, Choh Fei YEAP
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Publication number: 20150194525Abstract: A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film.Type: ApplicationFiled: May 5, 2014Publication date: July 9, 2015Applicant: QUALCOMM IncorporatedInventors: Jeffrey Junhao XU, Vladimir MACHKAOUTSAN, Kern RIM, Stanley Seungchul SONG, Choh Fei YEAP
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Publication number: 20150194339Abstract: Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.Type: ApplicationFiled: May 20, 2014Publication date: July 9, 2015Applicant: QUALCOMM IncorporatedInventors: Stanley Seungchul SONG, Kern RIM, Zhongze WANG, Jeffrey Junhao XU, Xiangdong CHEN, Choh Fei YEAP
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Publication number: 20150145069Abstract: Methods for fabricating a fin in a fin field effect transistor (FinFET), include exposing a single crystal fin structure coupled to a substrate of the FinFET. The single crystal fin structure is of a first material. The method further includes implanting a second material into the exposed single crystal fin structure at a first temperature. The first temperature reduces amorphization of the single crystal fin structure. The implanted single crystal fin structure comprises at least 20% of the first material. The method also includes annealing the implanted fin structure at a second temperature. The second temperature reduces crystal defects in the implanted fin structure to form the fin.Type: ApplicationFiled: May 5, 2014Publication date: May 28, 2015Applicant: QUALCOMM IncorporatedInventors: Jeffrey Junhao XU, Choh Fei YEAP
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Publication number: 20150144962Abstract: A complementary fin field-effect transistor (FinFET) includes a p-type device having a p-channel fin. The p-channel fin may include a first material that is lattice mismatched relative to a semiconductor substrate. The first material may have a compressive strain. The FinFET device also includes an n-type device having an re-channel fin. The n-channel fin may include a second material having a tensile strain that is lattice mismatched relative to the semiconductor substrate. The p-type device and the n-type device cooperate to form the complementary FinFET device.Type: ApplicationFiled: July 2, 2014Publication date: May 28, 2015Inventors: Kern RIM, Jeffrey Junhao XU, Stanley Seungchul SONG
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Patent number: 8927377Abstract: A method includes forming a gate stack to cover a middle portion of a semiconductor fin, and doping an exposed portion of the semiconductor fin with an n-type impurity to form an n-type doped region. At least a portion of the middle portion is protected by the gate stack from receiving the n-type impurity. The method further includes etching the n-type doped region using chlorine radicals to form a recess, and performing an epitaxy to re-grow a semiconductor region in the recess.Type: GrantFiled: December 27, 2012Date of Patent: January 6, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeffrey Junhao Xu, Ziwei Fang, Ying Zhang
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Patent number: 8853025Abstract: An embodiment method of controlling threshold voltages in a fin field effect transistor (FinFET) includes forming a dummy gate over a central portion of a fin, the central portion of the fin disposed between exterior portions of the fin unprotected by the dummy gate, removing the exterior portions of the fin and replacing the exterior portions of the fin with an epitaxially-grown silicon-containing material, applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over the hard mask of the dummy gate, etching away the hard mask and a polysilicon of the dummy gate to expose a gate oxide of the dummy gate, the gate oxide disposed over the central portion of the fin, and implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin.Type: GrantFiled: February 8, 2013Date of Patent: October 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying Zhang, Ziwei Fang, Jeffrey Junhao Xu
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Publication number: 20140264494Abstract: A method includes depositing a first metal layer on a native SiO2 layer that is disposed on at least one of a source and a drain of a metal-oxide-semiconductor field-effect transistor (MOSFET). A metal oxide layer is formed from the native SiO2 layer and the first metal layer, wherein the remaining first metal layer, the metal oxide layer, and the at least one of the source and the drain form a metal-insulator-semiconductor (MIS) contact.Type: ApplicationFiled: May 24, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Jeffrey Junhao Xu
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Patent number: 8809171Abstract: A method includes forming a first and a second gate stack to cover a first and a second middle portion of a first and a second semiconductor fin, respectively, and performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region, respectively. A portion of each of the first and the second middle portions is protected from the implantations. The first n-type doped region and the second n-type doped region have different gate proximities from edges of the first gate stack and the second stack, respectively. The first and the second n-type doped regions are etched using chlorine radicals to form a first and a second recess, respectively. An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively.Type: GrantFiled: January 23, 2013Date of Patent: August 19, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeffrey Junhao Xu, Ying Zhang, Ziwei Fang
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Publication number: 20140227850Abstract: An embodiment method of controlling threshold voltages in a fin field effect transistor (FinFET) includes forming a dummy gate over a central portion of a fin, the central portion of the fin disposed between exterior portions of the fin unprotected by the dummy gate, removing the exterior portions of the fin and replacing the exterior portions of the fin with an epitaxially-grown silicon-containing material, applying a spin-on resist over the dummy gate and the epitaxially-grown silicon-containing material and then removing the spin-on resist over the hard mask of the dummy gate, etching away the hard mask and a polysilicon of the dummy gate to expose a gate oxide of the dummy gate, the gate oxide disposed over the central portion of the fin, and implanting ions into the central portion of the fin through the gate oxide disposed over the central portion of the fin.Type: ApplicationFiled: February 8, 2013Publication date: August 14, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying Zhang, Ziwei Fang, Jeffrey Junhao Xu
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Publication number: 20140187011Abstract: A method includes forming a gate stack to cover a middle portion of a semiconductor fin, and doping an exposed portion of the semiconductor fin with an n-type impurity to form an n-type doped region. At least a portion of the middle portion is protected by the gate stack from receiving the n-type impurity. The method further includes etching the n-type doped region using chlorine radicals to form a recess, and performing an epitaxy to re-grow a semiconductor region in the recess.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jeffrey Junhao Xu, Ziwei Fang, Ying Zhang
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Publication number: 20140187013Abstract: A method includes forming a first and a second gate stack to cover a first and a second middle portion of a first and a second semiconductor fin, respectively, and performing implantations to implant exposed portions of the first and the second semiconductor fins to form a first and a second n-type doped region, respectively. A portion of each of the first and the second middle portions is protected from the implantations. The first n-type doped region and the second n-type doped region have different gate proximities from edges of the first gate stack and the second stack, respectively. The first and the second n-type doped regions are etched using chlorine radicals to form a first and a second recess, respectively. An epitaxy is performed to re-grow a first semiconductor region and a second semiconductor region in the first recess and the second recess, respectively.Type: ApplicationFiled: January 23, 2013Publication date: July 3, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jeffrey Junhao Xu, Ying Zhang, Ziwei Fang
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Patent number: 8703565Abstract: An integrated circuit structure includes a substrate and a germanium-containing semiconductor fin over the substrate. The germanium-containing semiconductor fin has an upper portion having a first width, and a neck region under the upper portion and having a second width smaller than the first width.Type: GrantFiled: March 11, 2013Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hao Chang, Jeffrey Junhao Xu, Chien-Hsun Wang, Chih-Hsiang Chang