Patents by Inventor Jeffrey P. Kubala

Jeffrey P. Kubala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10908903
    Abstract: A system and method of implementing a wait state for a plurality of threads executing on a computer processor core of the processor. The processor is configured to execute instruction streams by the plurality of threads, wherein the plurality of threads includes a first thread and a set of remaining threads and determine that the first thread has entered a first wait state loop. The processor is also configured to determine that any of the set of remaining threads has not entered a corresponding wait state loop and remain by the first thread in the first wait state loop until each of the set of remaining threads has entered the corresponding wait state loop.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
  • Patent number: 10628347
    Abstract: Described herein are technical features for freeing a buffer used during execution of a work-item by a multiprocessor. An example method includes identifying a first processing unit that assigned the buffer to the work-item, in response to a request from a second processing unit to free the buffer. The computer-implemented method also includes identifying a bitmap associated with the buffer, the bitmap being in a local memory of the first processing unit. The computer-implemented method also includes updating a bit from the bitmap to indicate that the buffer has been freed, the bit corresponding to the buffer.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Kubala, Jerry A. Moody, Muruganandam Somasundaram
  • Patent number: 10621007
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, Donald W. Schmidt
  • Publication number: 20190317828
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, Donald W. Schmidt
  • Patent number: 10372505
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, Donald W. Schmidt
  • Publication number: 20190155762
    Abstract: Described herein are technical features for freeing a buffer used during execution of a work-item by a multiprocessor. An example method includes identifying a first processing unit that assigned the buffer to the work-item, in response to a request from a second processing unit to free the buffer. The computer-implemented method also includes identifying a bitmap associated with the buffer, the bitmap being in a local memory of the first processing unit. The computer-implemented method also includes updating a bit from the bitmap to indicate that the buffer has been freed, the bit corresponding to the buffer.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 23, 2019
    Inventors: Jeffrey P. Kubala, Jerry A. Moody, Muruganandam Somasundaram
  • Patent number: 10282327
    Abstract: Testing for pending external interruptions. A Test Pending External Interruption instruction tests for pending external interruptions. The test for pending external interruptions is based on one or more program-specified subclasses, regardless of whether the machine is enabled for those classes of interruption. The instruction provides an indication for those subclasses being tested of whether there are any pending external interruptions for those subclasses.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Dan F. Greiner, Jeffrey P. Kubala, James H. Mulder, Timothy J. Slegel
  • Patent number: 10235310
    Abstract: Described herein are technical features for freeing a buffer used during execution of a work-item by a multiprocessor. An example method includes identifying a first processing unit that assigned the buffer to the work-item, in response to a request from a second processing unit to free the buffer. The computer-implemented method also includes identifying a bitmap associated with the buffer, the bitmap being in a local memory of the first processing unit. The computer-implemented method also includes updating a bit from the bitmap to indicate that the buffer has been freed, the bit corresponding to the buffer.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Kubala, Jerry A. Moody, Muruganandam Somasundaram
  • Patent number: 10223301
    Abstract: Aspects of the present invention include a method, system and computer program product that implements a memory management scheme for each processor in a multiprocessor system. The method includes pre-allocating, for each processor in a multiprocessor system, a set of memory buffers; and implementing a metadata bitmap for each pre-allocated set of memory buffers, wherein the metadata bitmap for each pre-allocated set of memory buffers comprises a plurality of bits, and wherein each of the plurality of bits is indicative of a usage state of a corresponding one of the memory buffers within each pre-allocated set of memory buffers.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Kubala, Jerry A. Moody, Muruganandam Somasundaram
  • Patent number: 10210109
    Abstract: Aspects of the present invention include a method, system and computer program product that implements a memory management scheme for each processor in a multiprocessor system. The method includes pre-allocating, for each processor in a multiprocessor system, a set of memory buffers; and implementing a metadata bitmap for each pre-allocated set of memory buffers, wherein the metadata bitmap for each pre-allocated set of memory buffers comprises a plurality of bits, and wherein each of the plurality of bits is indicative of a usage state of a corresponding one of the memory buffers within each pre-allocated set of memory buffers.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Kubala, Jerry A. Moody, Muruganandam Somasundaram
  • Patent number: 10209912
    Abstract: Examples of techniques for pre-allocating save areas of memory of a computer processing system are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include initiating, by a host processing device, a control program. The method may further include, responsive to initiating the control program, pre-allocating, by the host processing device, a plurality of save areas for each of a plurality of processors, wherein the plurality of save areas are anchored in a fixed area of the memory for each of the plurality of processors.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Kubala, Jerry A. Moody, Muruganandam Somasundaram
  • Publication number: 20190004867
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.
    Type: Application
    Filed: August 14, 2018
    Publication date: January 3, 2019
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, Donald W. Schmidt
  • Patent number: 10061623
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: August 28, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S Farrell, Charles W Gainey, Jeffrey P Kubala, Donald W Schmidt
  • Patent number: 10055261
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S Farrell, Charles W Gainey, Jr., Jeffrey P. Kubala, Donald W Schmidt
  • Publication number: 20180203814
    Abstract: Testing for pending external interruptions. A Test Pending External Interruption instruction tests for pending external interruptions. The test for pending external interruptions is based on one or more program-specified subclasses, regardless of whether the machine is enabled for those classes of interruption. The instruction provides an indication for those subclasses being tested of whether there are any pending external interruptions for those subclasses.
    Type: Application
    Filed: January 19, 2017
    Publication date: July 19, 2018
    Inventors: Mark S. Farrell, Dan F. Greiner, Jeffrey P. Kubala, James H. Mulder, Timothy J. Slegel
  • Publication number: 20180173446
    Abstract: Examples of techniques for pre-allocating save areas of memory of a computer processing system are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include initiating, by a host processing device, a control program. The method may further include, responsive to initiating the control program, pre-allocating, by the host processing device, a plurality of save areas for each of a plurality of processors, wherein the plurality of save areas are anchored in a fixed area of the memory for each of the plurality of processors.
    Type: Application
    Filed: February 14, 2018
    Publication date: June 21, 2018
    Inventors: Jeffrey P. Kubala, Jerry A. Moody, Muruganandam Somasundaram
  • Publication number: 20180150223
    Abstract: Aspects of the present invention include a method, system and computer program product that implements a memory management scheme for each processor in a multiprocessor system. The method includes pre-allocating, for each processor in a multiprocessor system, a set of memory buffers; and implementing a metadata bitmap for each pre-allocated set of memory buffers, wherein the metadata bitmap for each pre-allocated set of memory buffers comprises a plurality of bits, and wherein each of the plurality of bits is indicative of a usage state of a corresponding one of the memory buffers within each pre-allocated set of memory buffers.
    Type: Application
    Filed: February 10, 2017
    Publication date: May 31, 2018
    Inventors: Jeffrey P. Kubala, Jerry A. Moody, Muruganandam Somasundaram
  • Publication number: 20180150417
    Abstract: Described herein are technical features for freeing a buffer used during execution of a work-item by a multiprocessor. An example method includes identifying a first processing unit that assigned the buffer to the work-item, in response to a request from a second processing unit to free the buffer. The computer-implemented method also includes identifying a bitmap associated with the buffer, the bitmap being in a local memory of the first processing unit. The computer-implemented method also includes updating a bit from the bitmap to indicate that the buffer has been freed, the bit corresponding to the buffer.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Inventors: JEFFREY P. KUBALA, JERRY A. MOODY, MURUGANANDAM SOMASUNDARAM
  • Publication number: 20180150416
    Abstract: Aspects of the present invention include a method, system and computer program product that implements a memory management scheme for each processor in a multiprocessor system. The method includes pre-allocating, for each processor in a multiprocessor system, a set of memory buffers; and implementing a metadata bitmap for each pre-allocated set of memory buffers, wherein the metadata bitmap for each pre-allocated set of memory buffers comprises a plurality of bits, and wherein each of the plurality of bits is indicative of a usage state of a corresponding one of the memory buffers within each pre-allocated set of memory buffers.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Inventors: Jeffrey P. Kubala, Jerry A. Moody, Muruganandam Somasundaram
  • Publication number: 20180107495
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.
    Type: Application
    Filed: July 17, 2014
    Publication date: April 19, 2018
    Inventors: Mark S. Farrell, Charles W. Gainey, Jeffrey P. Kubala, Donald W. Schmidt