Patents by Inventor Jeffrey P. Kubala

Jeffrey P. Kubala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8458714
    Abstract: The configuration of the logical processors of a logical partition is managed dynamically. A logical partition is initially configured with one or more logical processors. Thereafter, the configuration can be dynamically adjusted. This dynamic adjustment may be in response to workload of the logical partition.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Gary M. King, Jeffrey P. Kubala, Jeffrey M. Nick, Peter B. Yocom, Daniel A. Kaberon
  • Publication number: 20130014123
    Abstract: An embodiment provides for operating an information processing system. An aspect of the invention includes allocating an execution interval to a first logical processor of a plurality of logical processors of the information processing system. The execution interval is allocated for use by the first logical processor in executing instructions on a physical processor of the information processing system. The first logical processor determines that a resource required for execution by the first logical processor is locked by another one of the other logical processors. An instruction is issued by the first logical processor to determine whether a lock-holding logical processor is currently running. The lock-holding logical processor waits to release the lock if it is currently running. A command is issued by the first logical processor to a super-privileged process for relinquishing the allocated execution interval by the first logical processor if the locking holding processor is not running.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg A. Dyck, Mark S. Farrell, Charles W. Gainey, Jeffrey P. Kubala, Robert R. Rogers, Mark A. Wisniewski
  • Patent number: 8352950
    Abstract: A method and apparatus for use in a computing environment to run a variety of applications in logical partitions. The apparatus includes one or more logical processors (LPs), one or more logical partitions (LPARs) configured to each access a share of processing resources of the LPs in accordance with predefined instructions, and an LPAR manager configured to determine an operational mode of each of the LPARs and any available amount of an excess of the share of the processing resources of the LPs and to dispatch the processing resources of at least a subset of the LPs to the LPARs in accordance with the respective predetermined shares and with respect to the determined operational mode of the respective LPARs and the amount, if any, of the excess share.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: January 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Donna N. Dillenberger, Jeffrey P. Kubala, Bernard Pierce, Donald W. Schmidt
  • Patent number: 8301815
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of quest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Mark S Farrell, Charles W Gainey, Jeffrey P Kubala, Donald W Schmidt
  • Patent number: 8281315
    Abstract: Exemplary embodiments include a system and storage medium for managing computer processing functions in a multi-processor computer environment. The system includes a physical processor, a standard logical processor, an assist logical processor sharing a same logical partition as the standard logical processor, and a single operating system instance associated with the logical partition, the single operating system instance including a switch-to service and a switch-from service. The system also includes a dispatch component managed by the single operating system instance. Upon invoking the switch-to service by standard code, the switch-to service checks to see if an assist logical processor is online and, if so, it updates an integrated assist field of a work element block associated with the task for indicating the task is eligible to be executed on the assist logical processor. The switch-to service also assigns a work queue to the work element block.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: October 2, 2012
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Ault, Jose R. Castano, Jeffrey P. Kubala, Robert J. Maddison, Bernard R. Pierce, Gary S. Puchkoff, Peter J. Relson, Robert R. Rogers, Donald W. Schmidt, Leslie W. Wyman
  • Patent number: 8276155
    Abstract: Exemplary embodiments include a system and storage medium for managing computer processing functions in a multi-processor computer environment. The system includes a physical processor, a standard logical processor, an assist logical processor sharing a same logical partition as the standard logical processor, and a single operating system instance associated with the logical partition, the single operating system instance including a switch-to service and a switch-from service. The system also includes a dispatch component managed by the single operating system instance. Upon invoking the switch-to service by standard code, the switch-to service checks to see if an assist logical processor is online and, if so, it updates an integrated assist field of a work element block associated with the task for indicating the task is eligible to be executed on the assist logical processor. The switch-to service also assigns a work queue to the work element block.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Donald F. Ault, Jose R. Castano, Jeffrey P. Kubala, Robert J. Maddison, Bernard R. Pierce, Gary S. Puchkoff, Peter J. Relson, Robert R. Rogers, Donald W. Schmidt, Leslie W. Wyman
  • Patent number: 8276151
    Abstract: A method is provided for a first logical processor to determine a running status of a target logical processor of an information processing system. In such method, an instruction is issued by the first logical processor running on the information processing system for determining whether the target logical processor is running. In response to issuing the instruction, a state descriptor belonging to the target logical processor is queried to determine whether the target logical processor is currently running. A result is then returned to the first logical processor, the result indicating whether or not the target logical processor is currently running.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Greg A. Dyck, Mark S. Farrell, Charles W. Gainey, Jeffrey P. Kubala, Robert R. Rogers, Mark A. Wisniewski
  • Publication number: 20110283280
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of quest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.
    Type: Application
    Filed: July 29, 2011
    Publication date: November 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, Donald W. Schmidt
  • Publication number: 20110246752
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
    Type: Application
    Filed: June 15, 2011
    Publication date: October 6, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, Donald W. Schmidt
  • Patent number: 8015335
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: September 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, Donald W. Schmidt
  • Patent number: 7984275
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: July 19, 2011
    Assignee: International Business Machiness Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, Donald W. Schmidt
  • Publication number: 20110113434
    Abstract: Exemplary embodiments include a system and storage medium for managing computer processing functions in a multi-processor computer environment. The system includes a physical processor, a standard logical processor, an assist logical processor sharing a same logical partition as the standard logical processor, and a single operating system instance associated with the logical partition, the single operating system instance including a switch-to service and a switch-from service. The system also includes a dispatch component managed by the single operating system instance. Upon invoking the switch-to service by standard code, the switch-to service checks to see if an assist logical processor is online and, if so, it updates an integrated assist field of a work element block associated with the task for indicating the task is eligible to be executed on the assist logical processor. The switch-to service also assigns a work queue to the work element block.
    Type: Application
    Filed: January 20, 2011
    Publication date: May 12, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Donald F. Ault, Jose R. Castano, Jeffrey P. Kubala, Robert J. Maddison, Bernard R. Pierce, Gary S. Puchkoff, Peter J. Relson, Robert R. Rogers, Donald W. Schmidt, Leslie W. Wyman
  • Publication number: 20100223448
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
    Type: Application
    Filed: May 13, 2010
    Publication date: September 2, 2010
    Applicant: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, Donald W. Schmidt
  • Patent number: 7739434
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, Donald W. Schmidt
  • Patent number: 7734900
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, Donald W. Schmidt
  • Publication number: 20100095033
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization related to the amount of a host CPU resource is provided to a guest CPU.
    Type: Application
    Filed: December 11, 2009
    Publication date: April 15, 2010
    Applicant: International Business Machines Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, Donald W. Schmidt
  • Patent number: 7650469
    Abstract: A method is provided for determining whether a logical processor of an information processing system has access to an address space of the information processing system. An instruction is issued by a first processor, the instruction referencing a target logical processor and a target address space. In response to the instruction, first information is checked to determine whether the target logical processor is running. When it is determined that the target logical processor is not running, second information is checked by a host program to determine whether the target logical processor has access to the target address space.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: January 19, 2010
    Assignee: International Business Machines Corporation
    Inventors: Greg A. Dyck, Charles W. Gainey, Jeffrey P. Kubala, James H. Mulder, Damian L. Osisek, Robert R. Rogers, Mark A. Wisniewski, Leslie W. Wyman
  • Patent number: 7587531
    Abstract: An input/output subsystem is configured as a plurality of input/output subsystem images, each of which appears to a program as an independent input/output subsystem. An input/output subsystem image is identified by an input/output subsystem image identifier, which is used by various programs to designate the particular input/output subsystem image for which an I/O operation is to be performed. An input/output subsystem image includes, for instance, one or more input/output paths. An input/output path of an input/output subsystem image is identified by an input/output path identifier, as well as a physical input/output path identifier.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: September 8, 2009
    Assignee: International Business Machines Corporation
    Inventors: Frank W. Brice, Jr., Janet R. Easton, Charles W. Gainey, Jr., Steven G. Glassen, Beth Glendening, Marten J. Halma, Jeffrey P. Kubala, Hans-Helge Lehmann, Tan Lu, Allan S. Meritt, Kenneth J. Oakes, Charles E. Shapley, John S. Trotter, Leslie W. Wyman, Harry M. Yudenfriend
  • Publication number: 20090183166
    Abstract: A method and apparatus for use in a computing environment to run a variety of applications in logical partitions. The apparatus includes one or more logical processors (LPs), one or more logical partitions (LPARs) configured to each access a share of processing resources of the LPs in accordance with predefined instructions, and an LPAR manager configured to determine an operational mode of each of the LPARs and any available amount of an excess of the share of the processing resources of the LPs and to dispatch the processing resources of at least a subset of the LPs to the LPARs in accordance with the respective predetermined shares and with respect to the determined operational mode of the respective LPARs and the amount, if any, of the excess share.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 16, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Donna N. Dillenberger, Jeffrey P. Kubala, Bernard Pierce, Donald W. Schmidt
  • Publication number: 20090182979
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
    Type: Application
    Filed: January 11, 2008
    Publication date: July 16, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, Donald W. Schmidt