Patents by Inventor Jeffrey P. Kubala
Jeffrey P. Kubala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9417876Abstract: Embodiments relate to thread context restoration. One aspect is a multithreading computer system including a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context.Type: GrantFiled: March 27, 2014Date of Patent: August 16, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Patent number: 9389862Abstract: Embodiments relate to thread context restoration. One aspect is a multithreading computer system including a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context.Type: GrantFiled: March 27, 2014Date of Patent: July 12, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Patent number: 9354883Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.Type: GrantFiled: March 27, 2014Date of Patent: May 31, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa Cranton Heller, Christian Jacobi, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20160110195Abstract: A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads.Type: ApplicationFiled: October 20, 2014Publication date: April 21, 2016Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa C. Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20160110218Abstract: A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads.Type: ApplicationFiled: September 3, 2015Publication date: April 21, 2016Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Dan F. Greiner, Lisa C. Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20160103774Abstract: A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.Type: ApplicationFiled: October 8, 2014Publication date: April 14, 2016Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa C. Heller, Christian Jacobi, Jeffrey P. Kubala, Frank Lehnert, Bernd Nerz, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Patent number: 9262236Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.Type: GrantFiled: July 30, 2015Date of Patent: February 16, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
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Patent number: 9223574Abstract: Embodiments relate to multithreading in a computer. An aspect is a computer including a configuration having a core which includes physical threads and is operable in single thread (ST) and multithreading (MT) modes. The computer also includes a host program configured to execute in the ST mode on the core to issue a start-virtual-execution (start-VE) instruction to dispatch a guest entity which includes a guest virtual machine (VM). The start-VE instruction is executed by the core and includes obtaining a state description, having a guest state, from a location specified by the start-VE instruction. The execution includes determining, based on the guest state, whether the guest entity includes a single guest thread or multiple guest threads, and starting the guest threads in the MT mode or ST mode based on the guest state and a determination of whether the guest entity includes a single guest thread or multiple guest threads.Type: GrantFiled: March 27, 2014Date of Patent: December 29, 2015Assignee: International Business Machines CorporationInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa Cranton Heller, Christian Jacobi, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Patent number: 9218185Abstract: Embodiments relate to multithreading capability information retrieval. An aspect is a computer system includes a configuration with one or more cores configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of each core. The computer system also includes a multithreading facility configured to control utilization of the configuration to perform a method that includes executing, by the core, a retrieve multithreading capability information instruction. The execution includes obtaining thread identification information that identifies multithreading capability of the configuration, and storing the obtained thread identification information.Type: GrantFiled: March 27, 2014Date of Patent: December 22, 2015Assignee: International Business Machines CorporationInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20150355940Abstract: Embodiments relate to idle time accumulation in a multithreading computer system. According to one aspect, a computer-implemented method for idle time accumulation in a computer system is provided. The computer system includes a configuration having a plurality of cores and an operating system (OS)-image configurable between single thread (ST) mode and a multithreading (MT) mode in a logical partition. The MT mode supports multiple threads on shared resources per core simultaneously. The method includes executing a query instruction on an initiating core of the plurality of cores. The executing includes obtaining, by the OS-image, a maximum thread identification value indicating a current maximum thread identifier of the cores within the logical partition. The initiating core also obtains a multithreading idle time value for each of the cores indicating an aggregate amount of idle time of all threads enabled on each of the cores in the MT mode.Type: ApplicationFiled: August 18, 2015Publication date: December 10, 2015Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20150355908Abstract: Embodiments relate to address expansion and contraction in a multithreading computer system. According to one aspect, a computer implemented method for address adjustment in a configuration is provided. The configuration includes a core configurable between an ST mode and an MT mode, where the ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The primary thread is accessed in the ST mode using a core address value. Switching from the ST mode to the MT mode is performed. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value. The expanded address value includes the core address value concatenated with a thread address value.Type: ApplicationFiled: August 18, 2015Publication date: December 10, 2015Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20150347132Abstract: According to one aspect, a computer-implemented method for thread context preservation in a configuration including a core configurable between a single thread (ST) mode and a multithreading (MT) mode is provided. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. Based on determining, by the core in the MT mode, that MT is to be disabled, switching from the MT mode to the ST mode is performed, where the primary thread of the MT mode is maintained as the primary thread of the ST mode. A thread context including program accessible register values and program counter values of the one or more secondary threads is made inaccessible to programs. Based on the switching, any one of clearing the program accessible register values or retaining the program accessible register values is performed.Type: ApplicationFiled: August 6, 2015Publication date: December 3, 2015Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damien L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20150339121Abstract: Embodiments relate to thread context restoration. One aspect is a multithreading computer system including a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context.Type: ApplicationFiled: August 6, 2015Publication date: November 26, 2015Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20150339120Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer-implemented method for dynamic enablement of multithreading in a configuration is provided. The configuration includes a core configurable between a single thread (ST) mode and a multithreading (MT) mode, where the ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.Type: ApplicationFiled: August 6, 2015Publication date: November 26, 2015Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Christian Jacobi, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20150339174Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.Type: ApplicationFiled: July 30, 2015Publication date: November 26, 2015Inventors: Mark S. Farrell, Charles W. Gainey, JR., Jeffrey P. Kubala, James H. Mulder, Bernard Pierce, Robert R. Rogers, Donald W. Schmidt
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Publication number: 20150277920Abstract: Embodiments relate to thread context restoration. One aspect is a multithreading computer system including a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Applicant: International Business Machines CorporationInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20150277948Abstract: Embodiments relate to a control area for managing multiple threads in a computer. An aspect is a computer system that includes a virtual machine (VM) configuration with one or more cores. Each core is enabled to operate in a single thread (ST) mode or a multithreading (MT) mode. The ST mode consists of a single thread and the MT mode consists of a plurality of threads on shared resources of a respective core. The computer system includes a core-oriented system control area (COSCA) having a common area representing all of the cores of the VM configuration and separate core description areas for each of the cores in the VM configuration. Each core description area indicates a location of one or more thread description areas each representing a thread within the respective core, and each thread description area indicates a location of a state description of the respective thread.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Applicant: International Business Machines CorporationInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20150277921Abstract: Embodiments relate to address expansion and contraction in a multithreading computer system. According to one aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Applicant: International Business Machines CorporationInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20150277908Abstract: Embodiments relate to multithreading in a computer. An aspect is a computer including a configuration having a core which includes physical threads and is operable in single thread (ST) and multithreading (MT) modes. The computer also includes a host program configured to execute in the ST mode on the core to issue a start-virtual-execution (start-VE) instruction to dispatch a guest entity which includes a guest virtual machine (VM). The start-VE instruction is executed by the core and includes obtaining a state description, having a guest state, from a location specified by the start-VE instruction. The execution includes determining, based on the guest state, whether the guest entity includes a single guest thread or multiple guest threads, and starting the guest threads in the MT mode or ST mode based on the guest state and a determination of whether the guest entity includes a single guest thread or multiple guest threads.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Applicant: International Business Machines CorporationInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Christian Jacobi, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel
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Publication number: 20150277913Abstract: Embodiments relate to multithreading capability information retrieval. An aspect is a computer system includes a configuration with one or more cores configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of each core. The computer system also includes a multithreading facility configured to control utilization of the configuration to perform a method that includes executing, by the core, a retrieve multithreading capability information instruction. The execution includes obtaining thread identification information that identifies multithreading capability of the configuration, and storing the obtained thread identification information.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Applicant: International Business Machines CorporationInventors: Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, JR., Dan F. Greiner, Lisa Cranton Heller, Jeffrey P. Kubala, Damian L. Osisek, Donald W. Schmidt, Timothy J. Slegel