Patents by Inventor Jeffrey Peter Gambino

Jeffrey Peter Gambino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220367534
    Abstract: An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 17, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter GAMBINO, David T. PRICE, Marc Allen SULFRIDGE, Richard MAURITZSON, Michael Gerard KEYES, Ryan RETTMANN, Kevin MCSTAY
  • Publication number: 20220271118
    Abstract: An integrated circuit die includes a silicon chromium (SiCr) thin film resistor disposed on a first oxide layer. The SiCr thin film resistor has a resistor body and a resistor head. A second oxide layer overlays the SiCr thin film resistor. The second oxide layer has an opening exposing a surface of the resistor head. A metal pad is disposed in the opening in the second oxide layer and is contact with the surface of the resistor head exposed by the opening. Further, an interlevel dielectric layer is disposed on the second oxide layer overlaying the SiCr thin film resistor. A metal-filled via extends from a top surface of interlevel dielectric layer through the interlevel dielectric layer and contacts the metal pad disposed in the opening in the second oxide layer.
    Type: Application
    Filed: February 25, 2021
    Publication date: August 25, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Rick Carlton JEROME, Gordon M. GRIVNA, Kevin Alexander STEWART, David T. PRICE, Jeffrey Peter GAMBINO
  • Publication number: 20220181462
    Abstract: In a general aspect, a transistor can include a fin having a proximal end and a distal end. The fin can include a dielectric portion longitudinally extending between the proximal end and the distal end, and a semiconductor layer disposed on the dielectric portion. The semiconductor layer can longitudinally extend between the proximal end and the distal end. The transistor can further include a source region disposed at the proximal end of the fin, and a drain region disposed at the distal end of the fin. The transistor can also include a gate dielectric layer disposed on a channel region of the semiconductor layer. The channel region can be disposed between the gate dielectric layer and the dielectric portion. The channel region can be longitudinally disposed between the source region and the drain region. The transistor can further include a conductive gate electrode disposed on the gate dielectric layer.
    Type: Application
    Filed: December 3, 2020
    Publication date: June 9, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter GAMBINO, Kevin Alexander STEWART, Peter MOENS, David T. PRICE, Derryl ALLMAN
  • Patent number: 11120941
    Abstract: Implementations of methods of forming capacitors may include depositing a first metal layer over a substrate, forming a photoresist layer over the first metal layer, patterning the photoresist layer, patterning the first metal layer using the pattern of the photoresist layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the dielectric layer to form a metal-insulator-metal capacitor.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: September 14, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter Gambino, Bruce Greenwood, Angel Rodriguez
  • Patent number: 11075148
    Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: July 27, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter Gambino, David T. Price, Jeffery A. Neuls, Dean E. Probst, Santosh Menon, Peter A. Burke, Bigildis Dosdos
  • Publication number: 20210215749
    Abstract: An event-recording circuit for recording electrical events experienced by an internal circuit in a semiconductor device is disclosed. The event-recording circuit is coupled to the internal circuit via a spark gap circuit. The spark gap circuit includes one or more encapsulated air-gap structures that are fabricated using a process flow that matches, or is adapted from, a process flow used in fabricating the semiconductor device. The event-recording circuit further includes a recording device that has an electrical property that is changed by a signal passed by the spark gap circuit, such as an ESD or EOS signal. Accordingly, a test may be performed to determine the presence, and in some cases the extent, of the change to the electrical property in a failure analysis of the semiconductor device.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 15, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter GAMBINO, Gavin HALL, Thomas F. LONG, Renaud André Jean Albert GILLON, Santosh MENON
  • Publication number: 20210111106
    Abstract: A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.
    Type: Application
    Filed: November 6, 2019
    Publication date: April 15, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter GAMBINO, David T. Price, Jeffery A. NEULS, Dean E. PROBST, Santosh MENON, Peter A. BURKE, Bigildis DOSDOS
  • Publication number: 20210111102
    Abstract: A method includes etching a through-substrate via (TSV) in a substrate from a backside of the substrate. The substrate has a device layer on a frontside. The method further includes depositing a conformal spacer layer on the backside of the substrate, and sidewalls and a bottom of the TSV, and etching the spacer layer to form a self-aligned mask for etching a contact opening at the bottom of TSV to a metal pad in the device layer, and etching the contact opening at the bottom of TSV to the metal pad in the device layer. The method further includes disposing a conductive material layer in the TSV and the contact opening to make a vertical interconnection from the backside of the substrate to the metal pad in the device layer.
    Type: Application
    Filed: October 5, 2020
    Publication date: April 15, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter GAMBINO, Swarnal BORTHAKUR
  • Patent number: 10978415
    Abstract: Implementations of semiconductor packages may include a first die including a plurality of contact pads, a second die including a plurality of contact pads, a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die, and a plurality of magnetic particles each coated in an oxide included in each of the plurality of solder interconnects.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: April 13, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter Gambino, Thomas F. Long
  • Publication number: 20210005566
    Abstract: Implementations of semiconductor packages may include a first die including a plurality of contact pads, a second die including a plurality of contact pads, a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die, and a plurality of magnetic particles each coated in an oxide included in each of the plurality of solder interconnects.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 7, 2021
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter GAMBINO, Thomas F. LONG
  • Publication number: 20200350271
    Abstract: Implementations of a semiconductor package may include: a first wafer having a first surface and a first set of blade interconnects, the first set of blade interconnects extending from the first surface. The package may include a second wafer having a first surface and a second set of blade interconnects, the second set of blade interconnects extending from the first surface and oriented substantially perpendicularly to a direction of orientation of the first set of blade interconnects. The first set of blade interconnects may be hybrid bonded to the second set of blade interconnects at a plurality of points of intersection between the first and second set of blade interconnects. The plurality of points of intersection may be located along a length of each blade interconnect of the first set of blade interconnects, and along the length of each blade interconnect of the second set of blade interconnects.
    Type: Application
    Filed: July 15, 2020
    Publication date: November 5, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Thomas Fairfax LONG, Jeffrey Peter GAMBINO, Charles Alvah HILL
  • Publication number: 20200328271
    Abstract: Implementations of capacitors may include: a first electrode having a first side and a second side. The capacitor may also include a silicon nitride (SiN) layer including on the second side of the first electrode. An opening may be included in the silicon nitride layer. The capacitors may include a dielectric layer within the opening of the SiN layer. The dielectric layer may include a recess. The capacitor may also include a second electrode having a first side and a second side. The first side of the second electrode may be included within the recess of the dielectric layer.
    Type: Application
    Filed: July 9, 2019
    Publication date: October 15, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter GAMBINO, David T. PRICE, Akihiro HASEGAWA, Derryl ALLMAN, Sallie J. HOSE, Kenneth Andrew BATES, Gregory Frank PIATT
  • Patent number: 10748864
    Abstract: Implementations of a semiconductor package may include: a first wafer having a first surface and a first set of blade interconnects, the first set of blade interconnects extending from the first surface. The package may include a second wafer having a first surface and a second set of blade interconnects, the second set of blade interconnects extending from the first surface and oriented substantially perpendicularly to a direction of orientation of the first set of blade interconnects. The first set of blade interconnects may be hybrid bonded to the second set of blade interconnects at a plurality of points of intersection between the first and second set of blade interconnects. The plurality of points of intersection may be located along a length of each blade interconnect of the first set of blade interconnects, and along the length of each blade interconnect of the second set of blade interconnects.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: August 18, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Thomas Fairfax Long, Jeffrey Peter Gambino, Charles Alvah Hill
  • Publication number: 20190393257
    Abstract: Implementations of image sensor devices may include a through-silicon-via (TSV) formed in a backside of an image sensor device and extending through a material of a die to a metal landing pad. The metal landing pad may be within a contact layer. The devices may include a TSV edge seal ring surrounding a portion of the TSV in the contact layer and extending from a first surface of the contact layer into the contact layer to a depth coextensive with a depth of the TSV.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter Gambino, Rick Jerome, David T. Price
  • Publication number: 20190363124
    Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.
    Type: Application
    Filed: August 9, 2019
    Publication date: November 28, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter GAMBINO, Kyle THOMAS, David T. PRICE, Rusty WINZENREAD, Bruce GREENWOOD
  • Patent number: 10431614
    Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: October 1, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter Gambino, Kyle Thomas, David T. Price, Rusty Winzenread, Bruce Greenwood
  • Patent number: 10403659
    Abstract: Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: September 3, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter Gambino, Angel Rodriguez, David T. Price, Jeffery Allen Neuls, Kenneth Andrew Bates, Rick Mauritzson
  • Publication number: 20190228908
    Abstract: Implementations of methods of forming capacitors may include depositing a first metal layer over a substrate, forming a photoresist layer over the first metal layer, patterning the photoresist layer, patterning the first metal layer using the pattern of the photoresist layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the dielectric layer to form a metal-insulator-metal capacitor.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 25, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter GAMBINO, Bruce GREENWOOD, Angel RODRIGUEZ
  • Publication number: 20190043903
    Abstract: Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.
    Type: Application
    Filed: August 29, 2018
    Publication date: February 7, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter GAMBINO, Angel RODRIGUEZ, David T. PRICE, Jeffery Allen NEULS, Kenneth Andrew BATES, Rick MAURITZSON
  • Patent number: 10090342
    Abstract: Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: October 2, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter Gambino, Angel Rodriguez, David T. Price, Jeffery Allen Neuls, Kenneth Andrew Bates, Rick Mauritzson