Abstract: Implementations of capacitors may include: a first electrode having a first side and a second side. The capacitor may also include a silicon nitride (SiN) layer including on the second side of the first electrode. An opening may be included in the silicon nitride layer. The capacitors may include a dielectric layer within the opening of the SiN layer. The dielectric layer may include a recess. The capacitor may also include a second electrode having a first side and a second side. The first side of the second electrode may be included within the recess of the dielectric layer.

Abstract: Implementations of a semiconductor package may include: a first wafer having a first surface and a first set of blade interconnects, the first set of blade interconnects extending from the first surface. The package may include a second wafer having a first surface and a second set of blade interconnects, the second set of blade interconnects extending from the first surface and oriented substantially perpendicularly to a direction of orientation of the first set of blade interconnects. The first set of blade interconnects may be hybrid bonded to the second set of blade interconnects at a plurality of points of intersection between the first and second set of blade interconnects. The plurality of points of intersection may be located along a length of each blade interconnect of the first set of blade interconnects, and along the length of each blade interconnect of the second set of blade interconnects.

Abstract: Implementations of image sensor devices may include a through-silicon-via (TSV) formed in a backside of an image sensor device and extending through a material of a die to a metal landing pad. The metal landing pad may be within a contact layer. The devices may include a TSV edge seal ring surrounding a portion of the TSV in the contact layer and extending from a first surface of the contact layer into the contact layer to a depth coextensive with a depth of the TSV.

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Abstract: Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.

Abstract: Implementations of methods of forming capacitors may include depositing a first metal layer over a substrate, forming a photoresist layer over the first metal layer, patterning the photoresist layer, patterning the first metal layer using the pattern of the photoresist layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the dielectric layer to form a metal-insulator-metal capacitor.

Abstract: Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.

Abstract: Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.

Abstract: Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Abstract: Implementations of a semiconductor package may include: a first wafer having a first surface and a first set of blade interconnects, the first set of blade interconnects extending from the first surface. The package may include a second wafer having a first surface and a second set of blade interconnects, the second set of blade interconnects extending from the first surface and oriented substantially perpendicularly to a direction of orientation of the first set of blade interconnects. The first set of blade interconnects may be hybrid bonded to the second set of blade interconnects at a plurality of points of intersection between the first and second set of blade interconnects. The plurality of points of intersection may be located along a length of each blade interconnect of the first set of blade interconnects, and along the length of each blade interconnect of the second set of blade interconnects.

Abstract: A method for forming an electrical structure. The electrical structure comprises an interconnect structure and a substrate. The substrate comprises an electrically conductive pad and a plurality of wire traces electrically connected to the electrically conductive pad. The electrically conductive pad is electrically and mechanically connected to the interconnect structure. The plurality of wire traces comprises a first wire trace, a second wire trace, a third wire trace, and a fourth wire trace. The first wire trace and second wire trace are each electrically connected to a first side of the electrically conductive pad. The third wire trace is electrically connected to a second side of the electrically conductive pad. The fourth wire trace is electrically connected to a third side of said first electrically conductive pad. The plurality of wire traces are configured to distribute a current.

Abstract: A solid state image sensor, a method for fabricating the solid state image sensor and a design structure for fabricating the solid state image sensor structure include a substrate that in turn includes a photosensitive region. Also included within solid state image sensor is a non-planar reflector layer located over a side of the photosensitive region and the substrate opposite an incoming radiation side of the photosensitive region and the substrate. The non-planar reflector layer is shaped and positioned to reflect uncaptured incident radiation back into the photosensitive region while avoiding optical cross-talk with an additional photosensitive region laterally separated within the substrate.

Abstract: A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract: Semiconductor structures. The semiconductor structures include two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers or bonding them back to back utilizing an inter-substrate dielectric layer and a bonding layer between the buried oxide layers. The structures include contacts formed in the upper wafer to devices in the lower wafer and wiring levels formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, a first dielectric layer, an underfill layer, a first solder structure, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The first solder structure is formed within the first opening and over a portion of the top surface of said first dielectric layer. The second substrate is formed over and in contact with the underfill layer.

Abstract: A solid state image sensor, a method for fabricating the solid state image sensor and a design structure for fabricating the solid state image sensor structure include a substrate that in turn includes a photosensitive region. Also included within solid state image sensor is a non-planar reflector layer located over a side of the photosensitive region and the substrate opposite an incoming radiation side of the photosensitive region and the substrate. The non-planar reflector layer is shaped and positioned to reflect uncaptured incident radiation back into the photosensitive region while avoiding optical cross-talk with an additional photosensitive region laterally separated within the substrate.

Abstract: A solid state image sensor, a method for fabricating the solid state image sensor and a design structure for fabricating the solid state image sensor structure include a substrate that in turn includes a photosensitive region. Also included within solid state image sensor is a non-planar reflector layer located over a side of the photosensitive region and the substrate opposite an incoming radiation side of the photosensitive region and the substrate. The non-planar reflector layer is shaped and positioned to reflect uncaptured incident radiation back into the photosensitive region while avoiding optical cross-talk with an additional photosensitive region laterally separated within the substrate.

Abstract: A variable focal point lens includes a transparent tank, which comprises a transparent enclosure containing a transparent flexible membrane separating the inner volume of the transparent tank into an upper tank portion and a lower tank portion. The upper tank portion and the lower tank portion contain liquids having different indices of refraction. The transparent flexible membrane is electrostatically displaced to change the thicknesses of the first tank portion and the second tank portion in the path of the light, thereby shifting the focal point of the lens axially and/or laterally. The electrostatic displacement of the membrane may be effected by a fixed charge in the membrane and an array of enclosure-side conductive structures on the transparent enclosure, or an array of membrane-side conductive structures on the transparent membrane and an array of enclosure-side conductive structures.

Abstract: A microelectronic structure includes a dielectric layer located over a substrate. The dielectric layer is separated from a copper containing conductor layer by an oxidation barrier layer. The microelectronic structure also includes a manganese oxide layer located aligned upon a portion of the copper containing conductor layer not adjoining the oxidation barrier layer. A method for fabricating the microelectronic structure includes sequentially forming and sequentially planarizing within an aperture within a dielectric layer an oxidation barrier layer, a manganese containing layer (or alternatively a mobile and oxidizable material layer) and finally, a planarized copper containing conductor layer (or alternatively a base material layer comprising a material less mobile and oxidizable than the mobile and oxidizable material layer) to completely fill the aperture.