Patents by Inventor Jeffrey S. Brown
Jeffrey S. Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7005334Abstract: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116?) and then annealing the substrate so as to cause the regions of the lower portion (140?) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).Type: GrantFiled: May 14, 2004Date of Patent: February 28, 2006Assignee: International Business Machines CorporationInventors: Jeffrey S. Brown, Chung H. Lam, Randy W. Mann, Jeffery H. Oppold
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Patent number: 6997688Abstract: A centrifugal pump includes a housing having a housing cavity, an inlet, and an outlet. A pump shaft is located within the housing cavity. A radial bearing coaxially surrounds the pump shaft. The shaft and the radial bearing are rotatable with respect to one another. An impeller is positioned to receive a fluid from the inlet and to exhaust the fluid to the outlet. The impeller has a first magnet assembly. A rotor has a second magnet assembly spaced apart from the first magnet assembly. A primary container is interposed between the impeller and the rotor. The primary container is arranged to contain a pumped fluid. A drive shaft is associated with the rotor for rotating the rotor. A secondary container contains the pumped fluid if the primary container leaks. The secondary container supports a generally dry-running seal (e.g., non-lubricated seal) associated with the drive shaft. The seal is disposed axially from the primary container and has a stationary portion and a rotating portion.Type: GrantFiled: March 6, 2003Date of Patent: February 14, 2006Assignee: Innovative Mag-Drive, LLCInventors: Manfred P. Klein, Brian C. Ward, Jeffrey S. Brown, Scott A. McAloon, Peter E. Phelps
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Patent number: 6980481Abstract: A memory circuit generally comprising a bit cell, a sense amplifier, and a control circuit. The bit cell may be configured to generate a bit signal. The sense amplifier may be configured to generate a reset signal in response to sensing the bit signal. The control circuit may be configured to (i) set a control latch in response to a detection signal and (ii) reset the control latch in response to the reset signal, wherein the control latch is set while both the detection signal and the reset signal are in an asserted state.Type: GrantFiled: December 20, 2001Date of Patent: December 27, 2005Assignee: LSI Logic CorporatiionInventor: Jeffrey S. Brown
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Patent number: 6908291Abstract: An impeller for a magnetic-drive centrifugal pump includes a core for supporting a magnetic assembly of magnets. An inner barrier covers at least part of the magnets. The inner barrier hermetically isolates the magnetic assembly within the impeller. For example, in one embodiment the inner barrier may be sealed or hermetically connected to the core at one or more seams. An outer barrier overlies the inner barrier.Type: GrantFiled: July 19, 2002Date of Patent: June 21, 2005Assignee: Innovative Mag-Drive, LLCInventors: Manfred P. Klein, Jeffrey S. Brown, Scott A. McAloon
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Patent number: 6888187Abstract: A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.Type: GrantFiled: August 26, 2002Date of Patent: May 3, 2005Assignee: International Business Machines CorporationInventors: Jeffrey S. Brown, David M. Fried, Edward J. Nowak, Beth Ann Rainey
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Patent number: 6881672Abstract: A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has silicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.Type: GrantFiled: November 26, 2003Date of Patent: April 19, 2005Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Jeffrey S. Brown, Terence B. Hook, Randy W. Mann, Christopher S. Putnam, Mohammad I. Younus
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Patent number: 6876035Abstract: A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI.Type: GrantFiled: May 6, 2003Date of Patent: April 5, 2005Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Jeffrey S. Brown, Robert J. Gauthier, Jr., Jed H. Rankin, William R. Tonti
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Patent number: 6864136Abstract: A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.Type: GrantFiled: December 11, 2003Date of Patent: March 8, 2005Assignee: International Business Machines CorporationInventors: Jeffrey S. Brown, David M. Fried, Edward J. Nowak, Beth Ann Rainey
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Publication number: 20040251475Abstract: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).Type: ApplicationFiled: May 14, 2004Publication date: December 16, 2004Applicant: International Business Machines CorporationInventors: Jeffrey S. Brown, Chung H. Lam, Randy W. Mann, Jeffery H. Oppold
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Publication number: 20040251496Abstract: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).Type: ApplicationFiled: June 11, 2003Publication date: December 16, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey S. Brown, Chung H. Lam, Randy W. Mann, Jeffrey H. Oppold
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Patent number: 6825530Abstract: A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116′) and then annealing the substrate so as to cause the regions of the lower portion (140′) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).Type: GrantFiled: June 11, 2003Date of Patent: November 30, 2004Assignee: International Business Machines CorporationInventors: Jeffrey S. Brown, Chung H. Lam, Randy W. Mann, Jeffery H Oppold
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Publication number: 20040222488Abstract: A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI.Type: ApplicationFiled: May 6, 2003Publication date: November 11, 2004Applicant: International Business Machines CorporationInventors: Wagdi W. Abadeer, Jeffrey S. Brown, Robert J. Gauthier, Jed H. Rankin, William R. Tonti
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Patent number: 6815751Abstract: Capacitor structures that have increased capacitance without compromising cell area are provided as well as methods for fabricating the same. A first capacitor structure includes insulating material present in holes that are formed in a semiconductor substrate, where the insulating material is thicker on the bottom wall of each capacitor hole as compared to the sidewalls of each hole. In another capacitor structure, deep capacitor holes are provided that have an isolation implant region present beneath each hole.Type: GrantFiled: July 1, 2002Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Jeffrey S. Brown, Randy W. Mann
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Patent number: 6797592Abstract: A method of ion implantation is provided. The method comprising: providing a substrate; forming a masking image having a sidewall on the substrate; forming a blocking layer on the substrate and on the masking image; and performing a retrograde ion implant through the blocking layer into the substrate, wherein the blocking layer substantially blocks ions scattered at the sidewall of the masking layer.Type: GrantFiled: April 23, 2003Date of Patent: September 28, 2004Assignee: International Business Machines CorporationInventors: Jeffrey S. Brown, Bryant C. Colwill, Terence B. Hook, Dennis Hoyniak
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Patent number: 6792578Abstract: Disclosed is an improved hard macro design for use in an ASIC, which avoids undesirable buildup of electrostatic charge on a gate of an I/O transistor of the hard macro. The hard macro includes a port level metallic conductor of an I/O port positioned at a low level metalization layer and an electrical connection between the port level metallic conductor and a gate conductor of the I/O transistor. The electrical connection includes a first conducting section extending from the gate conductor to a top level metallic conductor at a highest level metalization layer and a second conducting section extending from the top level metallic conductor layer to the port level conductor. Antenna rule violations at the I/O port of the hard macro are eliminated due to the electrical connection between the top level metallic conductor and a diffusion region.Type: GrantFiled: June 11, 2001Date of Patent: September 14, 2004Assignee: LSI Logic CorporationInventors: Jeffrey S. Brown, Craig R. Chafin
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Patent number: 6778449Abstract: A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.Type: GrantFiled: July 1, 2002Date of Patent: August 17, 2004Assignee: International Business Machines CorporationInventors: Matthew J. Breitwisch, Jeffrey S. Brown, Randy W. Mann, Jeffrey H. Oppold
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Patent number: 6770907Abstract: A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.Type: GrantFiled: May 30, 2003Date of Patent: August 3, 2004Assignee: International Business Machines CorporationInventors: Wagdi W. Abadeer, Eric Adler, Jeffrey S. Brown, Robert J. Gauthier, Jr., Jonathan M. McKenna, Jed H. Rankin, Edward W. Sengle, William R. Tonti
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Publication number: 20040126969Abstract: A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.Type: ApplicationFiled: December 11, 2003Publication date: July 1, 2004Inventors: Jeffrey S. Brown, David M. Fried, Edward J. Nowak, Beth Ann Rainey
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Publication number: 20040113234Abstract: A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.Type: ApplicationFiled: December 9, 2003Publication date: June 17, 2004Inventors: Wagdi W. Abadeer, Erle Adler, Jeffrey S. Brown, Robert J. Gauthier, Jonathan M. McKenna, Jed H. Rankin, Edward W. Sengle, William R. Tonti
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Publication number: 20040110371Abstract: A selectively silicided semiconductor structure and a method for fabricating same is disclosed herein. The semiconductor structure has silicide present on the polysilicon line between the N+ diffusion or N+ active area and the P+ diffusion or active area at the N+/P+ junction of the polysilicon line, and silicide is not present on the N+ active area and the P+ active area. The presence of this selective silicidation creates a beneficial low-resistance connection between the N+ region of the polysilicon line and the P+ region of the polysilicon line. The absence of silicidation on the N+ and P+ active areas, specifically on the PFET and NFET structures, prevents current leakage associated with the silicidation of devices.Type: ApplicationFiled: November 26, 2003Publication date: June 10, 2004Inventors: Matthew J. Breitwisch, Jeffrey S. Brown, Terence B. Hook, Randy W. Mann, Christopher S. Putnam, Mohammad I. Younus