Patents by Inventor Jen-Chieh Lin

Jen-Chieh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240383100
    Abstract: A method includes depositing a slurry onto a polishing pad of a chemical mechanical polishing (CMP) station. A workpiece is polished and polishing by-products and slurry are removed from the polishing pad by a vacuum head. A CMP apparatus includes a polishing pad configured to rotate during a CMP process. The apparatus also includes a slurry dispenser configured to deposit a slurry onto a polishing surface of the polishing pad. The apparatus further includes a momentum vacuum assembly including a slotted opening facing the polishing surface of the polishing pad. The apparatus also includes a first suction line coupled to an upper portion of the momentum vacuum assembly and leading to a first vacuum source, the first suction line configured to transport polishing products which have been removed from the polishing pad through the slotted opening.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen Chieh Lai, Szu-Cheng Wang, Chun-Jui Chu
  • Publication number: 20240363364
    Abstract: A semiconductor structure includes a first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die; and a molding material encapsulating the first die, the first conductive vias, the second conductive vias and the third conductive vias. A first width of each of the plurality of first conductive vias, a second width of each of the plurality of second conductive vias and a third width of the plurality of third conductive vias are different from each other.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Inventors: JEN-FU LIU, MING HUNG TSENG, YEN-LIANG LIN, LI-KO YEH, HUI-CHUN CHIANG, CHENG-CHIEH WU
  • Patent number: 12124767
    Abstract: An audio player device includes a sound capturing unit, an audio speaker unit, a storage unit and a processing unit. The storage unit stores multiple environmental volume ranges, and multiple volume setting values respectively corresponding to the environmental volume ranges. The processing unit obtains an environmental volume based on environmental sound received by the sound capturing unit, and selects a volume setting value that corresponds to an environmental volume range which covers the environmental volume to be an automatically-determined volume setting value. Then, the processing unit controls an output volume of the audio speaker unit according to the automatically-determined volume setting value.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: October 22, 2024
    Assignee: HEALTH & LIFE CO., LTD.
    Inventors: Jen-Chien Chien, Jen-Chieh Lin
  • Patent number: 12119312
    Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.
    Type: Grant
    Filed: July 18, 2023
    Date of Patent: October 15, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Nan Lin, Wei-Tung Chang, Jen-Chieh Kao, Huei-Shyong Cho
  • Publication number: 20240312901
    Abstract: An interconnect structure including a contact via in an interlayer dielectric, a first conductive feature in a first dielectric layer, the first dielectric layer over the interlayer dielectric, a first liner in the first dielectric layer, the first liner comprising a first part in contact with a sidewall surface of the first conductive feature, and a second part in contact with a bottom surface of the first conductive feature. The interconnect structure includes a first cap layer in contact with a top surface of the first conductive feature, a second conductive feature in a second dielectric layer, the second dielectric layer over the first dielectric layer, a second liner in the second dielectric layer, wherein the first and second conductive features comprise a first conductive material, and the contact via, first liner, first cap layer, and second liner comprise a second conductive material chemically different than the first conductive material.
    Type: Application
    Filed: July 12, 2023
    Publication date: September 19, 2024
    Inventors: Chien CHANG, Yen-Chun LIN, Jen-Wei LIU, Chih-Han TSENG, Harry CHIEN, Cheng-Hui WENG, Chun-Chieh LIN, Hung-Wen SU, Ming-Hsing TSAI, Chih-Wei CHANG
  • Patent number: 12087597
    Abstract: A semiconductor structure includes a first die; a second die disposed over the first die; a plurality of first conductive vias adjacent to the first die. The semiconductor structure further includes a plurality of second conductive vias disposed over the first conductive vias, each of the second conductive vias corresponding to one of the first conductive vias; a plurality of third conductive vias disposed over the first die and adjacent to the second die; and a molding material encapsulating the first die, the second die, the first conductive vias, the second conductive vias and the third conductive vias. A stepped shape is formed around an interface between each of the first conductive vias and the corresponding one of the second conductive vias.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: September 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jen-Fu Liu, Ming Hung Tseng, Yen-Liang Lin, Li-Ko Yeh, Hui-Chun Chiang, Cheng-Chieh Wu
  • Patent number: 12080594
    Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 3, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-Lun Tsai, Huei-Wen Hsieh, Chun-Sheng Chen, Kai-Shiang Kuo, Jen-Wei Liu, Cheng-Hui Weng, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 12076831
    Abstract: A chemical mechanical polishing (CMP) apparatus is provided, including a polishing pad and a polishing head. The polishing pad has a polishing surface. The polishing head is configured to hold a wafer in contact with the polishing surface during the polishing process. The polishing head includes a retaining ring, at least one fluid channel, and a vacuum pump. The retaining ring is arranged along the periphery of the polishing head and configured to retain the wafer. The at least one fluid channel is provided inside the polishing head, wherein the retaining ring includes a bottom surface facing the polishing surface and a plurality of holes in fluid communication with the bottom surface and the at least one fluid channel. The vacuum pump is fluidly coupled to the at least one fluid channel.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chen Wei, Jheng-Si Su, Shih-Ho Lin, Jen-Chieh Lai, Chun-Chieh Chan
  • Patent number: 12069851
    Abstract: A transistor, a memory and a method of forming the same are disclosed. The transistor includes a gate dielectric layer (200) having an upper portion (200b) and a lower portion (200a). The upper portion (200b) is multi-layer structure having an increased thickness without changing a thickness of the lower portion (200a). In this way, gate-induced drain current leakage of the transistor can be mitigated at uncompromised performance thereof. Additionally, the upper portion (200b) designed as multi-layer structure having an increased thickness can facilitate flexible adjustment in parameters of the upper portion (200b). The memory device includes dielectric material layers (DL), which are formed in respective word line trenches and each have an upper portion and a lower portion. In addition, in both trench isolation structures (STI) and active areas (AA), the upper portion of the dielectric material layers (DL) has a thickness greater than a thickness of the lower portion.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 20, 2024
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chung-Yen Chou, Chih-Yuan Chen, Qinfu Zhang, Chao-Wei Lin, Chia-Yi Chu, Jen-Chieh Cheng, Jen-Kuo Wu, Huixian Lai
  • Publication number: 20240239275
    Abstract: Disclosed is a method of forming a vehicle interior component. In the method, a glass article is arranged on a forming surface of a forming surface. The glass article has a first major surface and a second major surface. The first major surface faces the forming surface, and the second major surface is opposite to the first major surface. The second major surface includes a region having a surface free energy of at least 35 mN/m. An adhesive is applied to the region of the second major surface of the glass article. The adhesive is contacted with a frame to attach the frame to the glass article.
    Type: Application
    Filed: May 13, 2022
    Publication date: July 18, 2024
    Inventors: Jen-Chieh Lin, Arlin Lee Weikel
  • Patent number: 11999135
    Abstract: Described herein are articles and methods of making articles, for example glass articles, comprising a thin sheet and a carrier, wherein the thin sheet and carrier are bonded together using a modification (coating) layer, for example a cationic polymer coating layer, and associated deposition methods, the carrier, or both, to control van der Waals, hydrogen and covalent bonding between the thin sheet and the carrier. The modification layer bonds the thin sheet and carrier together with sufficient bond strength to prevent delamination of the thin sheet and the carrier during high temperature (?600° C.) processing while also preventing formation of a permanent bond between the sheets during such processing.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 4, 2024
    Assignee: CORNING INCORPORATED
    Inventors: Kaveh Adib, Indrani Bhattacharyya, Pei-Chen Chiang, Hong-goo Choi, Dae youn Kim, Jen-Chieh Lin, Prantik Mazumder, Pei-Lien Tseng
  • Patent number: 11948792
    Abstract: Embodiments of a glass wafer for semiconductor fabrication processes are described herein. In some embodiments, a glass wafer includes: a glass substrate comprising: a top surface, a bottom surface opposing the top surface, and an edge surface between the top surface and the bottom surface; a first coating disposed atop the glass substrate, wherein the first coating is a doped crystalline silicon coating having a sheet-resistance of 100 to 1,000,000 ohm per square; and a second coating having one or more layers disposed atop the glass substrate, wherein the second coating comprises a silicon containing coating, wherein the glass wafer has an average transmittance (T) of less than 50% over an entire wavelength range of 400 nm to 1000 nm.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: April 2, 2024
    Assignee: CORNING INCORPORATED
    Inventors: Ya-Huei Chang, Karl William Koch, III, Jen-Chieh Lin, Jian-Zhi Jay Zhang
  • Publication number: 20230341986
    Abstract: Embodiments are related generally to display devices, and more particularly to displays or display tiles having electrodes that extend from a first surface to a second surface of a substrate.
    Type: Application
    Filed: September 23, 2020
    Publication date: October 26, 2023
    Inventors: Ya-Huei Chang, Daniel Wayne Levesque, JR., Jen-Chieh Lin, Lu Zhang
  • Patent number: 11777067
    Abstract: Display tiles comprising pixel elements on a first surface of a substrate connected by an electrode, a driver located opposite the first surface, and a connector wrapped around an edge surface of the substrate connecting the driver to the pixel elements. Displays comprised of display tiles and methods of manufacturing display tiles and displays are also disclosed.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: October 3, 2023
    Assignee: Corning Incorporated
    Inventors: Jiangwei Feng, Sean Matthew Garner, Jen-Chieh Lin, Robert George Manley, Timothy James Orsley, Richard Curwood Peterson, Michael Lesley Sorensen, Pei-Lien Tseng, Rajesh Vaddi, Lu Zhang
  • Publication number: 20230294382
    Abstract: A functional laminated glass article includes: a backer substrate; a flexible glass substrate comprising a thickness of no greater than 300 ?m, and laminated to the backer substrate with an adhesive; a plurality of conductive traces disposed on one or both of the backer substrate and the flexible glass substrate; and a plurality of electronic device elements disposed between the backer substrate and the flexible glass substrate and in contact with the plurality of conductive traces. Further, the adhesive encapsulates the conductive traces and the electronic device elements between the backer substrate and the flexible glass substrate.
    Type: Application
    Filed: June 25, 2021
    Publication date: September 21, 2023
    Inventors: Li-Wei Chou, Sean Matthew Garner, Jen-Chieh Lin, Pei-Lien Tseng
  • Publication number: 20230201994
    Abstract: A polishing head assembly for polishing of semiconductor wafers includes a polishing head and a cap. The polishing head has a recess along a bottom portion. The recess has a recessed surface. The cap is positioned within the recess. The cap includes an annular wall secured to the polishing head and a floor joined to the annular wall at a joint. The floor extends across the annular wall, and the floor has an upper surface and a lower surface. The upper surface is spaced from the recessed surface to form a chamber therebetween. A deformation resistance of a portion of the floor proximate the joint is weakened to allow the portion of the floor proximate the joint to deflect relative to the polishing head by a change of pressure in the chamber.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 29, 2023
    Inventors: Chih Yuan Hsu, Jen Chieh Lin, Chieh Hu, Wei Chang Huang, Yau-Ching Yang
  • Patent number: 11674161
    Abstract: The present invention relates to novel monooxygenases which are useful in the hydroxylation of aromatic hydrocarbons. They are particularly useful for the production of 1-naththol and 7-hydroxycoumarin from naphthol and 7-Ethoxycoumarin, respectively.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: June 13, 2023
    Assignee: Covestro Intellectual Property GmbH & Co. KG
    Inventors: Ruijing Guo, Jen-Chieh Lin, Sha Tao, Ying Qian, Chenggang Qiu, Kequan Chen, Kang Li
  • Publication number: 20220410340
    Abstract: A polishing head assembly for polishing of semiconductor wafers includes a polishing head and a cap. The polishing head has a top portion and a recess along a bottom portion. The recess has a recessed surface. Holes extend from the top portion through the recessed surface. The cap is positioned within the recess and the cap has an annular wall and a floor extending across the annular wall. The annular wall has apertures corresponding to the holes. The floor is spaced from the recessed surface to form a chamber therebetween. The polishing head assembly also includes a band that circumscribes a portion of the annular wall. The holes and the corresponding apertures receive fasteners to removably secure the annular wall to the recessed surface.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 29, 2022
    Inventors: Peter Daniel Albrecht, Chih Yuan Hsu, Jen Chieh Lin, Wei Chang Huang, Yau-Ching Yang
  • Publication number: 20220348652
    Abstract: Disclosed herein are recombinant antibodies exhibiting binding affinity to CD47 polypeptide. According to some embodiments of the present disclosure, the recombinant antibodies are capable of blocking the interaction of CD47 and signal receptor protein-alpha (SIRP?). Accordingly, also disclosed herein are pharmaceutical compositions comprising the recombinant antibodies, and uses thereof in the treatment CD47-related diseases.
    Type: Application
    Filed: April 22, 2022
    Publication date: November 3, 2022
    Applicant: AnTaimmu BioMed Co., Ltd.
    Inventors: San-Tai SHEN, Yueh-Liang TSOU, Jen-Chieh LIN, Chia-Chi LIU
  • Publication number: 20220300247
    Abstract: An audio player device includes a sound capturing unit, an audio speaker unit, a storage unit and a processing unit. The storage unit stores multiple environmental volume ranges, and multiple volume setting values respectively corresponding to the environmental volume ranges. The processing unit obtains an environmental volume based on environmental sound received by the sound capturing unit, and selects a volume setting value that corresponds to an environmental volume range which covers the environmental volume to be an automatically-determined volume setting value. Then, the processing unit controls an output volume of the audio speaker unit according to the automatically-determined volume setting value.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 22, 2022
    Inventors: Jen-Chien CHIEN, Jen-Chieh LIN