Patents by Inventor Jen-Chieh Lin
Jen-Chieh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8872286Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.Type: GrantFiled: August 22, 2011Date of Patent: October 28, 2014Assignee: United Microelectronics Corp.Inventors: Tsun-Min Cheng, Min-Chuan Tsai, Chih-Chien Liu, Jen-Chieh Lin, Pei-Ying Li, Shao-Wei Wang, Mon-Sen Lin, Ching-Ling Lin
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Patent number: 8828745Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.Type: GrantFiled: July 6, 2011Date of Patent: September 9, 2014Assignee: United Microelectronics Corp.Inventors: Wei-Che Tsao, Chia-Lin Hsu, Jen-Chieh Lin, Teng-Chun Tsai, Hsin-Kuo Hsu, Ya-Hsueh Hsieh, Ren-Peng Huang, Chih-Hsien Chen, Wen-Chin Lin, Yung-Lun Hsieh
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Patent number: 8759219Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.Type: GrantFiled: January 24, 2011Date of Patent: June 24, 2014Assignee: United Microelectronics Corp.Inventors: Ya-Hsueh Hsieh, Teng-Chun Tsai, Wen-Chin Lin, Hsin-Kuo Hsu, Ren-Peng Huang, Chih-Hsien Chen, Chih-Chin Yang, Hung-Yuan Lu, Jen-Chieh Lin, Wei-Che Tsao
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Publication number: 20130049141Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.Type: ApplicationFiled: August 22, 2011Publication date: February 28, 2013Inventors: Tsun-Min Cheng, Min-Chuan Tsai, Chih-Chien Liu, Jen-Chieh Lin, Pei-Ying Li, Shao-Wei Wang, Mon-Sen Lin, Ching-Ling Lin
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Publication number: 20130011938Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.Type: ApplicationFiled: July 6, 2011Publication date: January 10, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Che TSAO, Chia-Lin Hsu, Jen-Chieh Lin, Teng-Chun Tsai, Hsin-Kuo Hsu, Ya-Hsueh Hsieh, Ren-Peng Huang, Chih-Hsien Chen, Wen-Chin Lin, Yung-Lun Hsieh
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Publication number: 20120325019Abstract: A force sensing device and a force sensing system are provided. The force sensing device comprises at least one magnetic material layer and a force sensing layer which can move with respect to each other. The force sensing layer comprises two sensing elements. The first sensing element, disposed along a first axis of the magnetic material layer, generates a sensing signal varying with a first lateral force applied on the force sensing device. The first lateral force enables the first sensing element to move relatively with respect to the magnetic material layer along the first axis. The second sensing element, disposed along a second axis of the magnetic material layer, generates a sensing signal varying with a second lateral force applied on the force sensing device. The second lateral force enables the second sensing element to move relatively with respect to the magnetic material layer along the second axis.Type: ApplicationFiled: October 24, 2011Publication date: December 27, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yio-Wha Shau, Arvin Huang-Te Li, Gaung-Hui Gu, Bai-Kuang Hwang, Jen-Chieh Lin
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Publication number: 20120187563Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.Type: ApplicationFiled: January 24, 2011Publication date: July 26, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ya-Hsueh HSIEH, Teng-Chun Tsai, Wen-Chin Lin, Hsin-Kuo Hsu, Ren-Peng Huang, Chih-Hsien Chen, Chih-Chin Yang, Hung-Yuan Lu, Jen-Chieh Lin, Wei-Che Tsao
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Publication number: 20120048296Abstract: A cleaning method for a wafer is provided. First, a first cleaning process is performed wherein the first cleaning process includes providing a cleaning solution having a first concentration. Next, a second cleaning process is performed, wherein the second cleaning process includes providing the cleaning solution having a second concentration. The second concentration is substantially greater than the first concentration. Next, a post-cleaning process is performed to provide dilute water.Type: ApplicationFiled: August 26, 2010Publication date: March 1, 2012Inventors: Wen-Chin Lin, Kai-Chun Yang, Jen-Chieh Lin, Jeng-Yu Fang, Chia-Lin Hsu, Teng-Chun Tsai, Wei-Che Tsao
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Publication number: 20110291054Abstract: A formulation including: an organic semiconducting material; and a carrier liquid including at least one of: a first liquid of the formulas (III) or (II): or mixtures of formulas (III) and (II); and a second liquid of a saturated or unsaturated cyclic hydrocarbylene compound of the formula (I): where the respective R1-8, x, and n are as defined herein, and optionally a tertiary liquid carrier, as defined herein. Also disclosed are semiconducting articles prepared with the formulations as defined herein.Type: ApplicationFiled: April 25, 2011Publication date: December 1, 2011Inventors: Mingqian He, Jianfeng Li, Jen-Chieh Lin, James Robert Matthews, Weijun Niu, Michael Lesley Sorensen
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Patent number: 8017229Abstract: A polyurethane composite is disclosed comprising rigid polyurethane and foamed thereupon a flexible integral skin (surface pore closed) polyurethane foam, wherein the rigid polyurethane having a density range of 600 kg/m3 to 1200 kg/m3, a Shore A hardness range of 90 to 99, a Shore D hardness range of 40 to 80, a tensile strength range of 10MPa to 60 MPa, a flexural strength range of 20 MPa to 60 Mpa, a elastic flexural modulus range of 800 MPa to 2500 Mpa, an elongation rate at break of 10-100% and an elongation at break of 25-150%; wherein the flexible integral skin (surface pore closed) polyurethane foam having a density range of 60 kg/m3 to 200 kg/m3, a tensile strength of 60 kPa to 250 kPa, an elongation at break of 70-180%, a tearing strength of 130-220 N/m, a resilience of falling ball of 40-70%, IFD25% of 200-600 N and IFD65% of 600-1800 N.Type: GrantFiled: September 26, 2005Date of Patent: September 13, 2011Assignee: Bayer MaterialScience AGInventors: Chenxi Zhang, Jen-Chieh Lin, Chi-Kwong Chow, Xiang Wang
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Publication number: 20110189855Abstract: A method for cleaning a surface is disclosed. First, a substrate including Cu and a barrier layer is provided. Second, a first chemical mechanical polishing procedure is performed on the substrate. Then, a second chemical mechanical polishing procedure is performed on the barrier layer. The second chemical mechanical polishing procedure includes performing a main chemical mechanical polishing procedure to partially remove the barrier layer and performing a chemical buffing procedure on the substrate using a chemical solution which has a pH value of about 6 to about 8 to remove residues on the substrate after the main chemical mechanical polishing procedure. Later, a water rinsing procedure is performed on the substrate. Afterwards, a post clean procedure is performed on the substrate after the second chemical mechanical polishing procedure.Type: ApplicationFiled: February 3, 2010Publication date: August 4, 2011Inventors: Jen-Chieh Lin, Kai-Chun Yang, Chih-Yueh Li, Geng-Yu Fan, Jeng-Yu Fang, Teng-Chun Tsai, Chia-Lin Hsu
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Patent number: 7675088Abstract: A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a number of scan lines and a number of source lines are disposed on the substrate and define a number of pixel regions. A number of the storage capacitance lines are disposed on the substrate in a direction extending along the scan lines and across the pixel regions, wherein each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion. A number of patterned thin films are disposed on the storage capacitance lines and above the cross portion.Type: GrantFiled: October 22, 2008Date of Patent: March 9, 2010Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Jun-Yao Huang, Kuang-Cheng Fu, Jen-Chieh Lin, Chin-Lung Yeh
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Patent number: 7606443Abstract: The present invention relates to an interpolation method for enlarging an image, wherein the image is composed of plural scanning lines. Firstly, it selects four adjacent continuous pixels xk?1, xk, xk+1, and xk+2 which have the pixel values f(xk?1), f(xk), f(xk+1), and f(xk+2) respectively on each of the scanning lines; next, it determines three linear equations Lk?1, Lk, and Lk+1 according to every two adjacent pixel values f(xk?1) and f(xk), f(xk) and f(xk+1), and f(xk+1) and f(xk+2), respectively; then, it selects a pixel x to be interpolated between the pixel xk and the pixel xk+1; finally, it applies the pixel x to the three linear equations Lk?1, Lk, and Lk+1 to determine three candidate pixel values which are weighted and combined to obtain pixel value f(x) of the pixel x.Type: GrantFiled: February 6, 2006Date of Patent: October 20, 2009Assignee: Tatung CompanyInventors: Chun-Hsien Chou, Jen-Chieh Lin, Shu-Min Liau, Tsung-Hao Lee
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Publication number: 20090061553Abstract: A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a number of scan lines and a number of source lines are disposed on the substrate and define a number of pixel regions. A number of the storage capacitance lines are disposed on the substrate in a direction extending along the scan lines and across the pixel regions, wherein each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion. A number of patterned thin films are disposed on the storage capacitance lines and above the cross portion.Type: ApplicationFiled: October 22, 2008Publication date: March 5, 2009Applicant: Chunghwa Picture Tubes, LTD.Inventors: Jun-Yao Huang, Kuang-Cheng Fu, Jen-Chieh Lin, Chin-Lung Yeh
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Publication number: 20080261022Abstract: A polyurethane composite is disclosed comprising rigid polyurethane and foamed thereupon a flexible integral skin (surface pore closed) polyurethane foam, wherein the rigid polyurethane having a density range of 600 kg/m3 to 1200 kg/m3, a Shore A hardness range of 90 to 99, a Shore D hardness range of 40 to 80, a tensile strength range of 10 MPa to 60 MPa, a flexural strength range of 20 MPa to 60 Mpa, a elastic flexural modulus range of 800 MPa to 2500 Mpa, an elongation rate at break of 10-100% and an elongation at break of 25-150%; wherein the flexible integral skin (surface pore closed) polyurethane foam having a density range of 60 kg/m3 to 200 kg/m3, a tensile strength of 60 kPa to 250 kPa, an elongation at break of 70-180%, a tearing strength of 130-220 N/m, a resilience of falling ball of 40-70%, IFD25% of 200-600 N and IFD65% of 600-1800 N.Type: ApplicationFiled: September 26, 2005Publication date: October 23, 2008Inventors: Chenxi Zhang, Jen-Chieh Lin, Chi-Kwong Chow, Xiang Wang
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Patent number: 7381374Abstract: An immunoassay cartridge for sensing at least one analyte in a biological sample is disclosed. The immunoassay cartridge comprises a supporting plate, a reaction cavity made within the supporting plate and having at least one analyte-binding molecule immobilized therein, a sample receiving end connected to the reaction cavity to allow the biological sample to flow into the reaction cavity for forming at least one complex of the analyte and the analyte-binding molecule, a first package containing a recognizing molecule, a first channel communicating the first package and the reaction cavity to allow the recognizing molecule to flow into the reaction cavity for forming a first product of the complex and the complex-binding molecule, a second package containing a buffer solution and a second channel communicating the second package and the reaction cavity to allow the buffer solution to flow into the reaction cavity.Type: GrantFiled: September 22, 2004Date of Patent: June 3, 2008Inventors: Hsiao-Chung Tsai, Hsueh-Chin Lin, Jen-Chieh Lin
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Publication number: 20080054264Abstract: A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a plurality of scan lines and a plurality of source lines are disposed on the substrate and define a plurality of pixel regions. A plurality of the storage capacitance lines are disposed on the substrate in a direction extending along the scan lines and across the pixel regions, wherein each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion. A plurality of patterned thin films are disposed on the storage capacitance lines and above the cross portion.Type: ApplicationFiled: January 4, 2007Publication date: March 6, 2008Inventors: Jun-Yao Huang, Kuang-Cheng Fu, Jen-Chieh Lin, Chin-Lung Yeh
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Publication number: 20070053025Abstract: The present invention relates to an interpolation method for enlarging an image, wherein the image is composed of plural scanning lines. Firstly, it selects four adjacent continuous pixels xk?1, xk, xk+1, and xk+2 which have the pixel values f(xk?1), f(xk), f(xk+1), and f(xk+2) respectively on each of the scanning lines; next, it determines three linear equations Lk?1, Lk, and Lk+1 according to every two adjacent pixel values f(xk?1) and f(xk), f(xk) and f(xk+1), and f(xk+1) and f(xk+2), respectively; then, it selects a pixel x to be interpolated between the pixel xk and the pixel xk+1; finally, it applies the pixel x to the three linear equations Lk?1, Lk, and Lk+1 to determine three candidate pixel values which are weighted and combined to obtain pixel value f(x) of the pixel x.Type: ApplicationFiled: February 6, 2006Publication date: March 8, 2007Applicant: Tatung CompanyInventors: Chun-Hsien Chou, Jen-Chieh Lin, Shu-Min Liau, Tsung-Hao Lee
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Publication number: 20060063251Abstract: An immunoassay cartridge for sensing at least one analyte in a biological sample is disclosed. The immunoassay cartridge comprises a supporting plate, a reaction cavity made within the supporting plate and having at least one analyte-binding molecule immobilized therein, a sample receiving end connected to the reaction cavity to allow the biological sample to flow into the reaction cavity for forming at least one complex of the analyte and the analyte-binding molecule, a first package containing a recognizing molecule, a first channel communicating the first package and the reaction cavity to allow the recognizing molecule to flow into the reaction cavity for forming a first product of the complex and the complex-binding molecule, a second package containing a buffer solution and a second channel communicating the second package and the reaction cavity to allow the buffer solution to flow into the reaction cavity.Type: ApplicationFiled: September 22, 2004Publication date: March 23, 2006Inventors: Hsiao-Chung Tsai, Hsueh-Chin Lin, Jen-Chieh Lin
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Publication number: 20040244673Abstract: Novel microporous crystal morphologies are produced by combining a polar solute, a silicon or phosphorous source, and a structure directing agent. A premixed mixture of at least one surfactants and a hydrophobic solvent is added to the previously mixed three species and shaken to for a reverse microemulsion. The microemulsion is stirred overnight, at about room temperature and then iced for five to ten minutes. A metal source is added and vigorously shaken for about two minutes. The mixture is then aged for about two hours at about room temperature. After which, a mineralizer is added and the resultant mixture aged for about two hours at about room temperature. The mixture is then heated to about 100-220° C. The final novel product is then isolated.Type: ApplicationFiled: January 30, 2004Publication date: December 9, 2004Inventors: Matthew Z. Yates, Jen-Chieh Lin