Abstract: A temperature sensor includes a sensing portion, an electrical transmitting portion, and an insulating hardened portion. The electrical transmitting portion is connected to the sensing portion. The insulating hardened layer at least envelops the electrical transmitting portion. A fan with a temperature detecting function includes the temperature sensor, a fan frame, and an impeller. The fan frame includes an air inlet and an air outlet. The impeller is rotatably mounted between the air inlet and the air outlet. The sensing portion of the temperature sensor is securely suspended in one of the air inlet and the air outlet of the fan frame by the insulating hardened layer.

Abstract: A high silica content substrate, such as for a device, is provided. The substrate has a high silica content and is thin. The substrate may include a surface with a topography or profile that facilitates bonding with a conductive metal layer, such as a metal layer for a circuit or antenna. The substrate may be flexible, have high temperature resistance, very low CTE, high strength and/or be non-reactive. The substrate may be suitable for use in circuits intended for use in high temperature environments, low temperature environments, reactive environments, or other harsh environments. The substrate may be suitable for high frequency antenna applications.

Abstract: Glass substrate assemblies having low dielectric properties, electronic assemblies incorporating glass substrate assemblies, and methods of fabricating glass substrate assemblies are disclosed. In one embodiment, a substrate assembly includes a glass layer 110 having a first surface and a second surface, and a thickness of less than about 300 ?m. The substrate assembly further includes a dielectric layer 120 disposed on at least one of the first surface or the second surface of the glass layer. The dielectric layer has a dielectric constant value of less than about 3.0 in response to electromagnetic radiation having a frequency of 10 GHz. In some embodiments, the glass layer is made of annealed glass such that the glass layer has a dielectric constant value of less than about 5.0 and a dissipation factor value of less than about 0.003 in response to electromagnetic radiation having a frequency of 10 GHz.

Abstract: A process includes providing a base substrate and disposing a precursor on the base substrate. The precursor includes powdered particles of a first material and an organic binder. The process includes photo-thermally treating the precursor to form a light extraction layer. The photo-thermal treatment includes exposing the precursor to a flash lamp that is energized in pulses. The process further includes disposing an organic light emitting diode adjacent to the light extraction layer.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: Disclosed herein are methods for forming light-transmitting articles comprising depositing a layer comprising a second material on a substrate comprising a first material, and forming a patterned surface on the second material. The first and second materials can have different glass transition temperatures Tg and/or refractive indices n. Additional layers comprising a third material can also be formed over the patterned surface, the third material having a glass transition temperature Tg and refractive index n that may be the same or different from those of the first and second material. Light-transmitting articles formed by such methods, as well as display devices comprising such light-transmitting articles are also disclosed herein.

Abstract: A stylus includes a circuit module, a battery module electrically connected to the circuit module, and a fine adjustment module. The circuit module has a circuit board and a variable resistor mounted on the circuit board. The fine adjustment module has a conductor and a conductive refill movably contact with the conductor. The conductor is connected to the circuit board and is electrically connected to the variable resistor via the conductor and the circuit board. The resistance value of the variable resistor can be adjusted to cause the stylus to output a first signal strength through the conductive refill. The conductive refill can be moved with respect to the conductor to enable the stylus to have a signal strength, which is X˜Y % of the first signal strength (80?X?100 and 100<Y?120).

Abstract: A high silica content substrate, such as for a device, is provided. The substrate has a high silica content and is thin. The substrate may include a surface with a topography or profile that facilitates bonding with a conductive metal layer, such as a metal layer for a circuit or antenna. The substrate may be flexible, have high temperature resistance, very low CTE, high strength and/or be non-reactive. The substrate may be suitable for use in circuits intended for use in high temperature environments, low temperature environments, reactive environments, or other harsh environments. The substrate may be suitable for high frequency antenna applications.

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface. A semiconductor structure formed by said semiconductor process is also provided.

Abstract: A semiconductor process includes the following steps. A dielectric layer having a recess is formed on a substrate. A barrier layer is formed to cover the recess, thereby the barrier layer having two sidewall parts. A conductive layer is formed on the barrier layer by an atomic layer deposition process, thereby the conductive layer having two sidewall parts. The two sidewall parts of the conductive layer are pulled down. A conductive material fills the recess and has a part contacting the two sidewall parts of the barrier layer protruding from the two sidewall parts of the conductive layer, wherein the equilibrium potential difference between the barrier layer and the conductive layer is different from the equilibrium potential difference between the barrier layer and the conductive material. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract: One or more aspects relate to an article that includes a glass substrate having a first average strain-to-failure; and a crack mitigating layer disposed on a first major surface of the substrate forming a first interface. The article also includes a film disposed on the crack mitigating layer forming a second interface and having a second average strain-to-failure that is less than the first average strain-to-failure. Further, at least one of the first and second interfaces exhibits a moderate adhesion such that at least a portion of the crack mitigating layer experiences one or more of a cohesive failure and an adhesive failure at the interfaces when the article is strained to a strain level between the first average strain-to-failure and the second average strain-to-failure. In addition, the refractive index of the crack mitigating layer is between or the same as the refractive indices of the substrate and the film.

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface.

Abstract: The present invention pertains to the field of polyurethane, especially relates to an isocyanate-terminated prepolymer, the method for preparing the same and the use thereof. The present invention adjusts the reaction components and the ratios thereof to obtain an isocyanate-terminated prepolymer suitable for preparing flexible polyurethane foam under a relative low mold temperature. The method for preparing flexible polyurethane foam by using the isocyanate-terminated prepolymer provided in this present invention can reduce the mold temperature, production time and energy consumption, as well as to obtain a polyurethane flexible foam processing good physical and mechanical properties.

Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating depositions are substantially aligned with the top surface of the insulation.

Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Abstract: A via structure and a method of forming the same are provided. In the forming method of the present invention, a via is formed in a dielectric layer. Next, a U-shaped seed layer is formed in the via. After that, a conductive material is selectively formed in the via to form a conductive bulk layer in the via. Through the present invention, the purposes of effectively removing the overhang adjacent to the opening of the via and protecting the U-shaped seed layer in the via can be achieved.

Abstract: A method for manufacturing a semiconductor device and a device manufactured by the same are provided. According to the embodiment, a substrate having at least a first area with a plurality of first gates and a second area with a plurality of second gates is provided, wherein the adjacent first gates and the adjacent second gates separated by an insulation, and a top surface of the insulation has a plurality of recesses. Then, a capping layer is formed over the first gate, the second gates and the insulation, and filling the recesses. The capping layer is removed until reaching the top surface of the insulation, thereby forming the insulating depositions filling up the recesses, wherein the upper surfaces of the insulating deposition are substantially aligned with the top surface of the insulation.

Abstract: A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

Abstract: A formulation including: an organic semiconducting material; and a carrier liquid including at least one of: a first liquid of the formulas (III) or (II): or mixtures of formulas (III) and (II); and a second liquid of a saturated or unsaturated cyclic hydrocarbylene compound of the formula (I): where the respective R1-8, x, and n are as defined herein, and optionally a tertiary liquid carrier, as defined herein. Also disclosed are semiconducting articles prepared with the formulations as defined herein.