Abstract: Embodiments of the disclosure relate to a method for fabricating semiconductor-on-insulator (SemOI) electronic components. In the method, a device wafer is bonded to a handling wafer. The device wafer includes a semiconductor device layer and a buried oxide layer. A substrate is adhered to the handling wafer. The substrate is a glass or a ceramic, and bonding occurs at an interface between the semiconductor device layer and the substrate. Material is removed from the device wafer to expose the buried oxide layer. The substrate is debonded from the handling wafer so as to provide an SemOI electronic component including the substrate, the semiconductor device layer, and the buried oxide layer.

Abstract: A method of making a display area and a glass tile as well as a display area that includes the glass tile. Prior to assembling the glass tile into the array, an edge treatment is performed on the glass tile, the edge treatment increasing an edge strength of the glass tile, as measured by the four point bend test, to at least about 200 MPa. The edge treatment can, for example, include at least one of plasma jet treatment and protective material application.

Abstract: Embodiments of a glass wafer for semiconductor fabrication processes are described herein. In some embodiments, a glass wafer includes: a glass substrate comprising: a top surface, a bottom surface opposing the top surface, and an edge surface between the top surface and the bottom surface; a first coating disposed atop the glass substrate, wherein the first coating is a doped crystalline silicon coating having a sheet-resistance of 100 to 1,000,000 ohm per square; and a second coating having one or more layers disposed atop the glass substrate, wherein the second coating comprises a silicon containing coating, wherein the glass wafer has an average transmittance (T) of less than 50% over an entire wavelength range of 400 nm to 1000 nm.

Abstract: The invention relates to aliphatic amines, methods for preparing the same and use thereof, particularly their use in curing agents. The method for preparing an aliphatic amine comprises reacting a reaction composition comprising an amino acid and an amine compound capable of dissolving the amino acid to obtain the aliphatic amine, wherein the content ratio of the amino acid to the amine compound is 1:10000-1:1, preferably 1:100-1:2, most preferably 1:10-1:2. The method for preparing an aliphatic amine provided by the present invention has a high reaction rate, a high conversion rate of the amino acid, a high purity of the aliphatic product, a long catalyst life, and easy purification of the reaction product.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: A glass element having a thickness from 25 ?m to 125 ?m, a first primary surface, a second primary surface, and a compressive stress region extending from the first primary surface to a first depth, the region defined by a compressive stress ?I of at least about 100 MPa at the first primary surface. Further, the glass element has a stress profile such that it does not fail when it is subject to 200,000 cycles of bending to a target bend radius of from 1 mm to 20 mm, by the parallel plate method. Still further, the glass element has a puncture resistance of greater than about 1.5 kgf when the first primary surface of the glass element is loaded with a tungsten carbide ball having a diameter of 1.5 mm.

Abstract: Display tiles comprising pixel elements on a first surface of a substrate connected by an electrode, a driver located opposite the first surface, and a connector wrapped around an edge surface of the substrate connecting the driver to the pixel elements. Displays comprised of display tiles and methods of manufacturing display tiles and displays are also disclosed.

Abstract: Described herein are articles and methods of making articles, for example glass articles, comprising a thin sheet and a carrier, wherein the thin sheet and carrier are bonded together using a modification (coating) layer, for example a cationic polymer coating layer, and associated deposition methods, the carrier, or both, to control van der Waals, hydrogen and covalent bonding between the thin sheet and the carrier. The modification layer bonds the thin sheet and carrier together with sufficient bond strength to prevent delamination of the thin sheet and the carrier during high temperature (?600° C.) processing while also preventing formation of a permanent bond between the sheets during such processing.

Abstract: A method for improving touch performance of a capacitive touch screen with a non-rectangular shape is provided. The capacitive touch screen includes plural complete cells and at least one incomplete cell for sensing. The method includes: determining whether an active area of the incomplete cell is different from an active area of each of the complete cells; and performing a mutual capacitance compensation on the incomplete cell to compensate a mutual capacitance of the incomplete cell when the active area of the incomplete cell is different from the active area of each of the complete cells.

Abstract: A method for improving touch performance of a capacitive touch screen with a non-rectangular shape is provided. The capacitive touch screen includes plural complete cells and at least one incomplete cell for sensing. The method includes: determining whether an active area of the incomplete cell is different from an active area of each of the complete cells; and performing a mutual capacitance compensation on the incomplete cell to compensate a mutual capacitance of the incomplete cell when the active area of the incomplete cell is different from the active area of each of the complete cells.

Abstract: A process includes providing a base substrate and disposing a precursor on the base substrate. The precursor includes powdered particles of a first material and an organic binder. The process includes photo-thermally treating the precursor to form a light extraction layer. The photo-thermal treatment includes exposing the precursor to a flash lamp that is energized in pulses. The process further includes disposing an organic light emitting diode adjacent to the light extraction layer.

Abstract: A process includes providing a base substrate and disposing a precursor on the base substrate. The precursor includes powdered particles of a first material and an organic binder. The process includes photo-thermally treating the precursor to form a light extraction layer. The photo-thermal treatment includes exposing the precursor to a flash lamp that is energized in pulses. The process further includes disposing an organic light emitting diode adjacent to the light extraction layer.

Abstract: A process includes providing a base substrate and disposing a precursor on the base substrate. The precursor includes powdered particles of a first material and an organic binder. The process includes photo-thermally treating the precursor to form a light extraction layer. The photo-thermal treatment includes exposing the precursor to a flash lamp that is energized in pulses. The process further includes disposing an organic light emitting diode adjacent to the light extraction layer.

Abstract: A method for improving wafer surface uniformity is disclosed. A wafer including a first region and a second region is provided. The first region and the second region have different pattern densities. A conductive layer is formed on the wafer. A buffer layer is then formed on the conductive layer. The buffer layer is polished until the conductive layer is exposed. A portion of the conductive layer and the remaining buffer layer are etched away.

Abstract: A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.