Abstract: The present invention discloses a method of manufacturing a multi-chip stacking package. The characteristic of the invention is that after the alignment of the bumps of at least two chips, welded bumps will be generated in a high temperature welding to form a welded bump. Furthermore, one of the at least two chips may only provide bonding pad similar to the Under Bump Metallurgy and may not provide bumps, and using the bonding pad to be welded with the bump on another chip.

Abstract: A bumping process for chip scale packaging comprises: providing a chip, the chip having an active surface that has a plurality of bonding pads; sequentially forming an under bump metal (UBM) structure and a leaded bump thereon on each of the bonding pads, wherein the material of the leaded bumps is composed of tin and more than 85% of lead; forming a thermosetting plastic on the active surface that covers the leaded bumps; and grinding the surface of the thermosetting plastic to expose the leaded bumps.

Abstract: The present invention discloses a multi-chip module packaging device which has outward extension portions of under bump metallurgies (UBM) for satisfying the bonding area requirement during wire bonding operation. Therefore, chips have electrical connections with metal bonding wires welded on the extended portions for transmitting electrical signals between each other. That is, the number of circuit layers of the substrate used in the device can be reduced; furthermore save on the production cost.

Abstract: The present invention discloses a test method for the electrical characteristics of the bumps on wafer. That is, the bumps on the scribe lines and the bumps on the neighbor chips are in the status of electrical connections, therefore the electrical characteristics of the bumps on the neighboring chips could be verified by utilizing a probe to touch the bumps on the scribe lines. Because the bumps on the neighboring chips are not really contacted with the probe, the intact profile of the bumps on the neighboring chips certainly keeps the same.

Abstract: The present invention discloses a device for testing electrical characteristics of a chip, which is capable of verifying whether each chip can meet the requirement of the electrical specifications, and sort out the chips under the specifications. The invention utilizes a probe to contact the extension area of the under bump metallurgy to detect if the electrical characteristics of the chip can meet the requirement of the specifications. As the bumps on the chip do not actually contact the probe, the intact profile for the bumps on the chips can be assuredly kept so that the problem of voids existing in the melted bumps during reflow process can be avoided.

Abstract: The present invention relates to a flip chip package comprising a chip assembly, a substrate, and an underfill material. The chip assembly has at least one chip. Each chips has a plurality of bond pads formed on a bottom portion of the chip. Each bond pad has a first solder bump formed on the bond pad. The chips are packaged by molding compound to form the chip assembly. The chip assembly has a bottom surface exposing a portion of the first solder bumps. The substrate has a plurality of support pads formed on a top surface of the substrate. Each support pad has a second solder bump formed on the support pad. The first solder bumps electrically connect to the second solder bumps to support the chip assembly by the substrate. The underfill material fills into a gap between the bottom surface of the chip assembly and the top surface of the substrate so as to form the flip chip package.

Abstract: A semiconductor device having a bump electrode comprising a substrate having a dielectric layer formed thereon, an aluminum contact pad on the substrate wherein at least a portion of the aluminum contact pad is exposed through the dielectric layer on the substrate. The aluminum contact pad is provided with an under bump metallurgy including a aluminum layer formed on the exposed portion of the aluminum contact pad, a nickel-vanadium layer formed on the aluminum layer and a titanium layer formed on the nickel-vanadium layer. A gold bump formed on the titanium layer acts as the bump electrode.

Abstract: A semiconductor package includes a substrate panel, a chip, an upper package encapsulant, and a lower package encapsulant. The chip is mounted to the substrate panel and below a hole in the substrate panel. A number of wires interconnect the leads on the chip with the leads on the substrate panel. The upper package encapsulant is formed on the upper side of the substrate panel by filling molten liquid plastic material into an upper mold placed on the upper side of the substrate panel. The lower package encapsulant is formed on the underside of the substrate panel by filling molten liquid plastic material into a lower mold placed on the underside of the substrate panel.

Abstract: A bumping process for chip scale packaging comprises: providing a chip, the chip having an active surface that has a plurality of bonding pads; sequentially forming an under bump metal (UBM) structure and a leaded bump thereon on each of the bonding pads, wherein the material of the leaded bumps is composed of tin and more than 85% of lead; forming a thermosetting plastic on the active surface that covers the leaded bumps; and grinding the surface of the thermosetting plastic to expose the leaded bumps.

Abstract: A packaging process providing a die with C4 solder bumps and a polymer substrate first. It then jets the melted second solder onto each of the C4 solder bumps forming a second solder bump. After reflowing and leveling the solder bumps, the die is flipped and combined with the substrate. Then heat treatment proceeds with the combination of the die and the substrate forming a flip chip package with collapse-controlled solder bump on the polymer substrate.

Abstract: A semiconductor package includes a substrate panel, a chip, an upper package encapsulant, and a lower package encapsulant. The chip is mounted to the substrate panel and below a hole in the substrate panel. A number of wires interconnect the leads on the chip with the leads on the substrate panel. The upper package encapsulant is formed on the upper side of the substrate panel by filling molten liquid plastic material into an upper mold placed on the upper side of the substrate panel. The lower package encapsulant is formed on the underside of the substrate panel by filling molten liquid plastic material into a lower mold placed on the underside of the substrate panel.

Abstract: A flip-chip semiconductor device and a method for under filling the flip-chip semiconductor device are disclosed. The flip-chip semiconductor device is provided with a substrate and a die having a plurality of solder bumps for connecting to the substrate. Encapsulation material is under filled between the die and the substrate. The substrate has a non-mask area defied in a center portion thereof while the remaining surface area is covered by a solder mask. The non-mask area defines a hole in the center thereof so that the encapsulation material can be dispensed along all sides of the die to flow toward the non-mask area and stop when reaching the non-mask area whereby the encapsulation material does not block the hole and air between said die and the substrate is limited in a void formed around the hole and communicated with the atmosphere via the hole.

Abstract: A chip-scale semiconductor package mainly includes a semiconductor chip, a substrate and a package body. Said chip is attached onto said substrate by an adhesive layer. Said chip has a plurality of bonding pads formed thereon. Said adhesive layer has an aperture corresponding to the bonding pads of said chip such that the bonding pads can be exposed within an aperture. Said substrate has several through-holes respectively corresponding to the bonding pads of said chip and parts of the area around the edge of said chip for dispensing of encapsulant after the soldering of leads of said substrate to the bonding pads of said chip. The encapsulant dispensed into the through-holes can flow from the surface of said chip to the edge thereof. Said package body has one portion provided within the through-hole of said substrate and another portion provided around the edge of said chip whereby encapsulation process is accomplished without having to turn the whole semiconductor package device.