Abstract: A multi-chip stack package includes a substrate, a first chip, a second chip, a plurality of bumps, a plurality of junction interface bumps, a plurality of conductive wires, a filler material and an encapsulating material. The substrate has a plurality of first contacts and a plurality of second contacts thereon. The first chip is bonded to the substrate surface by the bumps positioned between the active surface of the first chip and the first contacts. The second chip is bonded to the first chip by the junction interface bumps positioned between the back surface of the first chip and the back surface of the second chip. The conductive wires electrically connect the active surface of the second chip and the second contacts. The filler material encloses the bumps and the junction interface bumps. The encapsulating material encloses the first chip, the second chip and the conductive wires.

Abstract: A fabrication method for PCBs. The method includes providing a substrate having a layout area and a periphery area around the layout area on a surface, forming a patterned wiring layer, having a bus line in the periphery area, a plurality of pads in the layout area, a plurality of bridge lines providing electrical connection between the pads, and a plating line electrically connecting the bus line and pads, overlying the substrate, forming a patterned solder mask over the substrate and wiring layer, the patterned solder mask having a plurality of first openings respectively exposing the pads and plating a metal layer respectively overlying the pads, forming a plurality of second openings respectively exposing the bridge lines between the pads, and removing the exposed bridge lines.

Abstract: The present invention provides a method of forming a plurality of bumps over a wafer. The wafer has a plurality of contact pads and a passivation layer thereon and the passivation layer exposes the contact pads. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The patterned adhesion layer and patterned metallic layer remain on top of the contact pads. A photoresist layer having a plurality of openings that expose the metallic layer is formed on the active surface of the wafer. A flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is performed to bond the solder block with the metallic layer. Finally, the flux material and the photoresist layer are removed.

Abstract: A bumpless assembly package mainly comprises a substrate, and a chip. The substrate has an upper surface and an opposite lower surface, a plurality of first contacts and a plurality of second contacts formed on the upper surface of the substrate, wherein one of the first contacts is electrically connected to one of the second contacts. The chip has an active surface and a boding pad formed on the active surface and is disposed in the opening, Moreover, an electrically conductive layer is disposed above the upper surface of the substrate and the active surface of the chip, and extended from the upper surface of the substrate to the active surface of the chip so as to electrically connect the chip and the substrate. In addition, a protective layer is provided to dispose above the electrically conductive layer and expose the second contacts so that the second contacts can electrically connect to external electronic devices.

Abstract: A multi-chip stack package includes a substrate, a first chip, a second chip, a plurality of bumps, a plurality ofjunction interface bumps, a plurality of conductive wires, a filler material and an encapsulating material. The substrate has a plurality of first contacts and a plurality of second contacts thereon. The first chip is bonded to the substrate surface by the bumps positioned between the active surface of the first chip and the first contacts. The second chip is bonded to the first chip by the junction interface bumps positioned between the back surface of the first chip and the back surface of the second chip. The conductive wires electrically connect the active surface of the second chip and the second contacts. The filler material encloses the bumps and the junction interface bumps. The encapsulating material encloses the first chip, the second chip and the conductive wires.

Abstract: A wafer-level package structure, applicable to a flip-chip arrangement on a carrier, which comprises a plurality of contact points, is described. This wafer-level package structure is mainly formed with a chip and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The conductive layer can further be arranged at a region outside the bonding pads on the chip as a heat sink to enhance the heat dissipation ability of the package.

Abstract: A method of forming pre-solders on a substrate is provided. Firstly, a substrate is provided. The substrate includes an upper surface and a lower surface. There are several metal circuits and a solder mask both on the upper and the lower surfaces. Each solder mask covers parts of the corresponding metal circuits and parts of the corresponding surface for exposing parts of several pads of the corresponding metal circuits. Then, a patterned photo-resist film is formed on the upper surface. The patterned photo-resist film has several openings for exposing the upper-surface pads. Afterwards, several metal materials are formed in the opening by printing. Thereon, the metal materials are reflown to form several pre-solders on the upper-surface pads. Finally, the patterned photo-resist film is removed.

Abstract: A semiconductor chip package mainly includes a semiconductor chip, a first dielectric layer disposed on the semiconductor chip, a plurality of conductive traces electrically connected to the semiconductor chip, a second dielectric layer disposed on the conductive traces and the first dielectric layer wherein a portion of the conductive traces are exposed from the second dielectric layer, and a plurality of contacts for external connection formed on the exposed portion of the conductive traces. The semiconductor chip has a surface including an active area, a dummy area surrounding the active area, and a plurality of bonding pads disposed on the active area. The bonding pads are electrically connected to the contacts by the conductive traces. The present invention further provides methods for manufacturing the semiconductor chip package.

Abstract: A method of forming bumps on the active surface of a silicon wafer. A first under-bump metallic layer is formed over the active surface of the wafer. A second under-bump metallic layer is formed over the first under-bump metallic layer. A portion of the second under-bump metallic layer is removed to expose the first under-bump metallic layer. A plurality of solder bumps is implanted onto the second under-bump metallic layer. The exposed first under-bump metallic layer is removed so that only the first under-bump metallic layer underneath the second under-bump metallic layer remains.

Abstract: Printed circuit boards and methods for fabricating the same. A via in a printed circuit board electrically connects to trace lines of the PCB, such that only one plating line is required to electrically connect a plating bus and the plating through hole. Thus, in an electroplating step, current can flow to fingers in the trace lines to plate an anti-oxidation metal layer thereon. The via is separated into several sub-vias to electrically isolate the plating line from trace lines and fingers, each of which connects to the plating line or the trace lines. Finally, at least one plating line remains, thus avoiding negative impact on electrical performance of an electronic device that uses the printed circuit board.

Abstract: The present invention discloses a test method for the electrical characteristics of the bumps on wafer. That is, the bumps on the scribe lines and the bumps on the neighbor chips are in the status of electrical connections, therefore the electrical characteristics of the bumps on the neighboring chips could be verified by utilizing a probe to touch the bumps on the scribe lines. Because the bumps on the neighboring chips are not really contacted with the probe, the intact profile of the bumps on the neighboring chips certainly keeps the same.

Abstract: A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at least with an opening that exposes the pre-formed bump.

Abstract: A fabrication method for PCBs. The method includes providing a substrate having a layout area and a periphery area around the layout area on a surface, forming a patterned wiring layer, having a bus line in the periphery area, a plurality of pads in the layout area, a plurality of bridge lines providing electrical connection between the pads, and a plating line electrically connecting the bus line and pads, overlying the substrate, forming a patterned solder mask over the substrate and wiring layer, the patterned solder mask having a plurality of first openings respectively exposing the pads and plating a metal layer respectively overlying the pads, forming a plurality of second openings respectively exposing the bridge lines between the pads, and removing the exposed bridge lines.

Abstract: The present invention discloses a multi-chip module packaging device which has outward extension portions of under bump metallurgies (UBM) for satisfying the bonding area requirement during wire bonding operation. Therefore, chips have electrical connections with metal bonding wires welded on the extended portions for transmitting electrical signals between each other. That is, the number of circuit layers of the substrate used in the device can be reduced; furthermore save on the production cost.

Abstract: A semiconductor device with a capability can prevent a burnt fuse pad from re-electrical connection, wherein the semiconductor device includes a bump pad and a fuse pad over a wafer. The fuse pad includes the burnt fuse pad having a gap for electrical isolation. The semiconductor device comprises a dielectric layer, disposed substantially above the burnt fuse pad and filling the gap, and a bump structure, disposed on the bump pad. The foregoing semiconductor device can further comprise a passivation layer, which exposes the bump pad and a portion of the burnt fuse pad. Wherein, the dielectric layer is over the passivation layer, covers the exposed portion of the burnt fuse pad and fills the gap.

Abstract: The present invention discloses a semiconductor package, wherein several chips can be packed thereinto. The present invention uses under bump metallurgies or bonding wires to connect the associated circuits of at least two chips in serial or in parallel. At least one slicing path is located between the at least two chips and a substrate is provided with an upper surface and a lower surface in which the upper surface is flip-chip bonded with the at least two chips.

Abstract: A wafer-level package structure, applicable to a flip-chip type arrangement on a carrier having a plurality of contact points is described. This wafer-level package structure comprises a chip having a protective layer and a plurality of bonding pads and a conductive layer. The conductive layer is arranged on the bonding pads of the chip as contact points. The wafer-level package structure can further include a heat sink to enhance the heat dissipation ability of the package structure.

Abstract: A method of forming a plurality of bumps over a wafer. The wafer has an active surface having a passivation layer and a plurality of contact pads thereon. The passivation layer exposes the contact pads on the active surface. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The adhesion layer and the metallic layer are patterned so that the adhesion layer and the metallic layer remain on top of the contact pads. A photoresist layer is formed on the active surface of the wafer. The photoresist layer has a plurality of openings that expose the metallic layer. Flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is carried out so that the solder block bonds with the metallic layer. Finally, the flux material and the photoresist layer are removed.

Abstract: The present invention provides a method of forming a plurality of bumps over a wafer. The wafer has a plurality of contact pads and a passivation layer thereon and the passivation layer exposes the contact pads. An adhesion layer is formed over the active surface of the wafer and covers both the contact pads and the passivation layer. A metallic layer is formed over the adhesion layer. The patterned adhesion layer and patterned metallic layer remain on top of the contact pads. A photoresist layer having a plurality of openings that expose the metallic layer is formed on the active surface of the wafer. A flux material is deposited into the openings and then a solder block is disposed into each of the openings. A reflow process is performed to bond the solder block with the metallic layer. Finally, the flux material and the photoresist layer are removed.

Abstract: The present invention discloses a device for testing electrical characteristics of a chip, which is capable of verifying whether each chip can meet the requirement of the electrical specifications, and sort out the chips under the specifications. The invention utilizes a probe to contact the extension area of the under bump metallurgy to detect if the electrical characteristics of the chip can meet the requirement of the specifications. As the bumps on the chip do not actually contact the probe, the intact profile for the bumps on the chips can be assuredly kept so that the problem of voids existing in the melted bumps during reflow process can be avoided.