Patents by Inventor Jen Yu

Jen Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240093024
    Abstract: A polymer is formed by capping a copolymer-graft-polylactone with an alcohol, wherein the copolymer is copolymerized from an anhydride monomer with a double bond, a monomer with a double bond, and an initiator. The polymer can be mixed with an organic solvent and pigment powder to form a dispersion. The dispersion can be mixed with a binder to form a paint.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 21, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Cha-Wen CHANG, Jen-Yu CHEN, Wan-Jung TENG, Wen-Pin CHUANG, Ruo-Han YU
  • Publication number: 20240087207
    Abstract: Disclosed herein are system, method, and computer program product embodiments for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Applicant: MediaTek Inc.
    Inventors: Po-Yu HUANG, Shih-Chin LIN, Jen-Jung CHENG, Tu-Hsiu LEE
  • Patent number: 11930318
    Abstract: An electronic device, including a first substrate, a partition wall structure, a pressurizing component, a second substrate, a shell, and multiple first conductive parts, is provided. The first substrate has a through hole, and a first surface and a second surface that are opposite to each other. The partition wall structure is disposed on the first surface and surrounds to form a first chamber. The pressurizing component is disposed on the partition wall structure and covers the first chamber. The pressurizing component includes at least a mass and a vibration membrane. The shell is disposed on the second substrate and jointly forms a second chamber with the second substrate. The first chamber is formed in the second chamber. The multiple first conductive parts are disposed between the first substrate and the second substrate. There is a gap between any two adjacent first conductive parts.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 12, 2024
    Assignee: Merry Electronics Co., Ltd.
    Inventors: Yueh-Kang Lee, Jen-Yi Chen, Kai-Yu Jiang
  • Patent number: 11927799
    Abstract: A data transmission system is disclosed. The data transmission system includes at least one signal processing device, at least one conversion device, at least one antenna device, and at least one flexible printed circuit board. The at least one signal processing device is configured to generate or receive at least one data. The at least one conversion device is configured to transform between the at least one data and an optical signal. The at least one antenna device is configured to obtain the at least one data according to the optical signal, and configured to receive or transmit the at least one data wirelessly. The at least one flexible printed circuit board includes at least one conductive layer and at least one optical waveguide layer. The at least one optical waveguide layer is configured to transmit the optical signal.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: March 12, 2024
    Inventors: Po-Kuan Shen, Chun-Chiang Yen, Chiu-Lin Yu, Kai-Lun Han, Jenq-Yang Chang, Mao-Jen Wu, Chao-Chieh Hsu
  • Patent number: 11930618
    Abstract: A liquid cooling head includes a bottom plate, a heat dissipation plate, a partition plate and an upper cover plate. The bottom plate includes an opening, and the heat dissipation plate, the partition plate and the upper cover plate are fixed to the bottom plate. The partition plate divides the opening into a plurality of cooling chambers, and each cooling chamber is equipped with a cooling liquid inlet, a cooling liquid outlet, a pump and an electric control device. The cooling liquid inlet and the cooling liquid outlet are formed in the upper cover plate, the pump is fluid-connected to the cooling liquid outlet, and the electric control device drives the pump to rotate, so that the cooling liquid flows through the cooling chamber to cool one heat source below the heat dissipation plate. In addition, a liquid cooling device with the liquid cooling head is also disclosed therein.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 12, 2024
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chien-Yu Chen, Tian-Li Ye, Jen-Hao Lin, Chien-An Chen
  • Publication number: 20240076422
    Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Inventors: Jing-Cherng TSAI, Jen-Long WU, Wen-Hao KANG, Kuei-Pin LIN, Jing-Yu LEE, Jun-Ye HONG, Zih-Yu SHIH, Cheng-Hung CHIANG, Gang-Wei SHEN, Yu-Chuan SUNG, Chung-Hua WENG, Hsing-Ya CHEN
  • Publication number: 20240076720
    Abstract: Provided herein are methods, systems, and compositions for determining a base in a polynucleotide. In various aspects, the methods, systems, and compositions presented herein are useful for performing 4-base, 5-base, or 6-base sequencing of polynucleotide molecules, for example, from liquid biopsy samples or wherein the base is a low frequency mutation.
    Type: Application
    Filed: February 9, 2023
    Publication date: March 7, 2024
    Inventors: Shankar BALASUBRAMANIAN, Jens FULLGRABE, Walraj Singh GOSAL, Joanna Dawn HOLBROOK, Sidong LIU, David MORLEY, Oliver NENTWICH, Tobias OST, Michael STEWARD, Albert VILELLA, Nicolas James WALKER, Shirong YU, Helen Rachel BIGNELL, Rita Santo SAN-BENTO
  • Patent number: 11923392
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Jen-Cheng Liu, Kazuaki Hashimoto, Ming-En Chen, Shyh-Fann Ting, Shuang-Ji Tsai, Wei-Chieh Chiang
  • Publication number: 20240068043
    Abstract: Provided is a method for diagnosing and monitoring progression of cancer or effectiveness of a therapeutic treatment. The method includes detecting a methylation level of at least one gene in a biological sample containing circulating free DNA. Also provided are primer pairs and probes for diagnosis or prognosis of cancer in a subject in need thereof.
    Type: Application
    Filed: March 1, 2022
    Publication date: February 29, 2024
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsing-Chen TSAI, Chong-Jen YU, Hsuan-Hsuan LU, Shu-Yung LIN, Yi-Jhen HUANG, Chen-Yuan DONG
  • Publication number: 20240071428
    Abstract: A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit. The input stage circuit generates a first input signal having a first voltage and a second input signal based on a third input signal. The switching circuit operates in response to a first control signal, and adjusts a voltage level of a first data line according to the first input signal and a voltage level of a second data line according to the second input signal. The first latch circuit is coupled to the switching circuit by the first data line and the second data line. The first latch circuit latches a data in response to the first control signal and a second control signal, and adjusts the voltage level of the first data line based on a second voltage different from the first voltage.
    Type: Application
    Filed: November 8, 2023
    Publication date: February 29, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hua-Hsin YU, Hung-Jen LIAO, Cheng-Hung LEE, Hau-Tai SHIEH
  • Publication number: 20240072736
    Abstract: An amplifier DC bias protection circuit includes an amplifier module, a filter module and a comparator module. The amplifier module converts an input signal into a non-inverting signal and an inverting signal. The filter module blocks AC signals in the non-inverting signal and the inverting signal, thereby providing a first DC bias signal and a second DC bias signal accordingly. The comparator module is configured to determine whether the absolute value of a DC bias difference signal is greater than a predetermined value, and output a determination signal for deactivating the amplifier module when the absolute value of the DC bias difference signal is greater than the predetermined value. The DC bias difference signal is associated with the voltage difference between the first DC bias signal and the second DC bias signal.
    Type: Application
    Filed: December 1, 2022
    Publication date: February 29, 2024
    Applicant: ACER INCORPORATED
    Inventors: Po-Jen Tu, Jia-Ren Chang, Kai-Meng Tzeng, Ming-Chun Yu
  • Publication number: 20240065390
    Abstract: Bands for wearable devices include multiple band retainers used to maintain engagement between an assembly (e.g., a pair) of bands. Some band retainers may be permanently affixed with the band at a certain location of the band, while other band retainers can be removable. The removable band retainers can be moved to different locations of the band, thus allowing the band retainer to retain another band at different locations. As a result, the assembly of bands can be used with different users, and in particular, users with different wrist sizes. Moreover, using multiple band retainers can provide an engagement force between the bands to withstand higher-impact events, such as swimming and diving. Additionally, bands and band retainers may include one or more liquid-resistant and corrosion-resistant materials.
    Type: Application
    Filed: August 18, 2023
    Publication date: February 29, 2024
    Inventors: Nicholas S. Brodine, Molly J. Anderson, Clement C. Tissandier, Osamu Yabe, Mengxi Zhao, Timothy S. Lui, Chia Tse Yeh, Kai-Yu Chung, Jen-Chun Hsu, Tatsuya Sano, Peng Li
  • Patent number: 11915743
    Abstract: A latch formed from a memory cell includes a clock input terminal configured to receive a clock signal, complementary first and second data terminals, and a latch circuit. The latch circuit has first and second inverters. The first inverter has an input terminal coupled to the first data terminal, and the second inverter has an input terminal coupled to the second data terminal. A first pass gate transistor is coupled between an output terminal of the second inverter and the first data terminal. A second pass gate transistor is coupled between an output terminal of the first inverter and the second data terminal. The first and second pass gate transistors each have a gate terminal coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
  • Patent number: 11901263
    Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
  • Patent number: 11903325
    Abstract: A memory device includes a substrate; an active area extending along a first direction on the substrate; a gate line traversing the active area and extending along a second direction that is not parallel to the first direction; a source doped region in the active area and on a first side of the gate line; a main source line extending along the first direction; a source line extension coupled to the main source line and extending along the second direction; a drain doped region in the active area and on a second side of the gate line that is opposite to the first side; and a data storage element electrically coupled to the drain doped region. The main source line is electrically connected to the source doped region via the source line extension.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: February 13, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ting Wu, Yan-Jou Chen, Cheng-Tung Huang, Jen-Yu Wang, Po-Chun Yang, Yung-Ching Hsieh, Jian-Jhong Chen, Bo-Chang Li
  • Patent number: 11881274
    Abstract: A program control circuit for an antifuse-type one time programming memory cell array is provided. When the program action is performed, the program control circuit monitors the program current from the memory cell in real time and increases the program voltage at proper time. When the program control circuit judges that the program current generated by the memory cell is sufficient, the program control circuit confirms that the program action is completed.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: January 23, 2024
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Chia-Fu Chang, Po-Ping Wang, Jen-Yu Peng
  • Patent number: 11858953
    Abstract: The invention provides compositions and methods for synthesis of phosphorylated organic compounds, including nucleoside triphosphates.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: January 2, 2024
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: John Chaput, Jen-Yu Liao, Saikat Bala
  • Publication number: 20230422525
    Abstract: A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die and a memory die are mounted on a top surface of the bottom substrate in a side-by-side fashion. The logic die may have a thickness not less than 125 micrometers. A connection structure is disposed between the bottom substrate and the top substrate around the logic die and the memory die to electrically connect the bottom substrate with the top substrate. A sealing resin fills in the gap between the bottom substrate and the top substrate and sealing the logic die, the memory die, and the connection structure in the gap.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 28, 2023
    Applicant: MEDIATEK INC.
    Inventors: Ta-Jen Yu, Wen-Chin Tsai, Isabella Song, Che-Hung Kuo, Hsing-Chih Liu, Tai-Yu Chen, Shih-Chin Lin, Wen-Sung Hsu
  • Publication number: 20230420337
    Abstract: Cooling covers including trapezoidal cooling chambers for cooling packaged semiconductor devices and methods of forming the same are disclosed. In an embodiment, a cooling cover for a semiconductor device includes an inlet; an outlet; and a cooling chamber in fluid communication with the inlet and the outlet, the cooling chamber having a trapezoidal shape in a cross-sectional view.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Chung-Jung Wu, Sheng-Tsung Hsiao, Jen Yu Wang, Tung-Liang Shao, Chih-Hang Tung
  • Patent number: D1010638
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 9, 2024
    Assignee: Compal Electronics, Inc.
    Inventors: Jen-Yu Chiang, Wang-Hung Yeh, Hsin-Chieh Fang, Shu-Hsien Chu, Jia-Sheng Chen