Patents by Inventor Jen Yu

Jen Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230132108
    Abstract: A mounting device includes a housing, a sliding structure, and a switch structure. The housing includes two tracks, an elastic element including a blocking rib, and a first clamping element. The sliding structure is movably disposed in the tracks and includes a second clamping element and a reverse rib. The switch structure is movably disposed on the sliding structure and includes a forward rib. When the sliding structure is in the installed position, a support frame is fastened between the first clamping element and the second clamping element, and the blocking rib prevents the sliding structure moving relative to the housing. When the switch structure is moved in a detaching direction, the forward rib pushes the blocking rib away from the reverse rib, to allow the sliding structure to move in the detaching direction relative to the housing.
    Type: Application
    Filed: October 27, 2021
    Publication date: April 27, 2023
    Inventor: JEN-YU LIANG
  • Patent number: 11637103
    Abstract: A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: April 25, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
  • Patent number: 11631629
    Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: April 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
  • Patent number: 11632865
    Abstract: A mounting device includes a housing, a sliding structure, and a switch structure. The housing includes two tracks, an elastic element including a blocking rib, and a first clamping element. The sliding structure is movably disposed in the tracks and includes a second clamping element and a reverse rib. The switch structure is movably disposed on the sliding structure and includes a forward rib. When the sliding structure is in the installed position, a support frame is fastened between the first clamping element and the second clamping element, and the blocking rib prevents the sliding structure moving relative to the housing. When the switch structure is moved in a detaching direction, the forward rib pushes the blocking rib away from the reverse rib, to allow the sliding structure to move in the detaching direction relative to the housing.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: April 18, 2023
    Assignee: AMBIT MICROSYSTEMS (SHANGHAI) LTD.
    Inventor: Jen-Yu Liang
  • Publication number: 20230073399
    Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.
    Type: Application
    Filed: November 17, 2022
    Publication date: March 9, 2023
    Applicant: MediaTek Inc.
    Inventors: Yen-Yao Chi, Nai-Wei Liu, Ta-Jen Yu, Tzu-Hung Lin, Wen-Sung Hsu, Shih-Chin Lin
  • Publication number: 20230046413
    Abstract: A semiconductor assembly package is provided. The semiconductor package assembly includes a system-on-chip (SOC) package, a memory package and a heat spreader. The SOC package includes a logic die and a first substrate. The logic die has pads on it. The first substrate is electrically connected to the logic die by the pads. The memory package includes a second substrate and a memory die. The second substrate has a top surface and a bottom surface. The memory die is mounted on the top surface of the second substrate and is electrically connected to the second substrate using bonding wires. The heat spreader is disposed between the SOC package and the memory package, wherein the heat spreader is in contact with a back surface of the logic die away from the pads.
    Type: Application
    Filed: July 15, 2022
    Publication date: February 16, 2023
    Inventors: Tai-Yu CHEN, Chin-Lai CHEN, Hsiao-Yun CHEN, Wen-Sung HSU, Haw-Kuen SU, Duen-Yi HO, Bo-Jiun YANG, Ta-Jen YU, Bo-Hao MA
  • Patent number: 11578154
    Abstract: A method for manufacturing a polymer emulsion includes the following steps. A mixture is heated to a first temperature less than or equal to about 40° C. The mixture including about 100 to about 500 parts by weight of a monomer and about 0.5 to about 95 parts by weight of a first cross-linking agent, in which the monomer has a structure of formula (I): and R1, R2, and R3 represent H or C1-C4 alkyl group, respectively. About 0.005 to about 5 parts by weight of a first initiator is added. About 0.003 to about 5 parts by weight of a reducing agent is added to form an intermediate product. The intermediate product is heated to a second temperature less than or equal to about 92° C.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: February 14, 2023
    Inventor: Jen-Yu Liu
  • Patent number: 11569147
    Abstract: A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Liang Shao, Jen-Yu Wang, Chung-Jung Wu, Chih-Hang Tung, Chen-Hua Yu
  • Publication number: 20230022794
    Abstract: The present invention provides a method for monitoring tracks and a track monitoring module. The method comprises: maintaining a target list, stored a target track, by a monitoring server; recording a first track related to a first mobile device by a first monitoring application; and comparing the similarity between the first track and the target track by the first monitoring application to generate a comparison result.
    Type: Application
    Filed: June 1, 2022
    Publication date: January 26, 2023
    Inventors: Yao-Tung Tsou, Juang-Ying Chueh, Jen-Yu Huang
  • Publication number: 20230015001
    Abstract: A projection apparatus including a projection device, a reflecting component, and an image capturing device is provided. The projection device is adapted to project an image light beam to form a projection image. The reflecting component is disposed on the projection device and has a reflecting surface. The image capturing device is disposed on the projection device and has an image capturing end. The image capturing end faces the reflecting surface. The reflecting surface is adapted to reflect the projection image to the image capturing end.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 19, 2023
    Applicant: Coretronic Corporation
    Inventors: Jen-Yu Shie, Kuang-Hsiang Chang, Hung-Pin Chen, Heng Li
  • Publication number: 20230007912
    Abstract: A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of the package substrate surrounding the semiconductor devices; a cover including silicon bonded to the package ring and covering the semiconductor devices; and a thermal interface structure (TIS) thermally connecting the semiconductor devices to the cover.
    Type: Application
    Filed: January 17, 2022
    Publication date: January 12, 2023
    Inventors: Jen Yu WANG, Chung-Jung WU, Sheng-Tsung HSIAO, Tung-Liang SHAO, Chih-Hang TUNG, Chen-Hua YU
  • Publication number: 20220399775
    Abstract: A fan module including a first casing, a second casing, a supporting assembly, a stator assembly, and a rotor assembly. The first casing includes a first vent. The second casing is connected to the first casing and an accommodating space is formed between the first casing and the second casing. The supporting assembly is disposed at the accommodating space, connected to the second casing, and includes a first end and a second end. The stator assembly is disposed at the accommodating space, fixed on the second casing, and disposed around the supporting assembly. The rotor assembly is disposed at the accommodating space, rotatably disposed around the stator assembly, and corresponding to the first vent. The first end of the supporting assembly passes through the rotor assembly and the first vent for protruding out of the first casing.
    Type: Application
    Filed: February 21, 2022
    Publication date: December 15, 2022
    Applicant: ASUSTeK COMPUTER INC.
    Inventor: Ching Jen Yu
  • Publication number: 20220392839
    Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.
    Type: Application
    Filed: August 12, 2022
    Publication date: December 8, 2022
    Applicant: MediaTek Inc.
    Inventors: Yen-Yao Chi, Nai-Wei Liu, Ta-Jen Yu, Tzu-Hung Lin, Wen-Sung Hsu
  • Publication number: 20220384523
    Abstract: A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.
    Type: Application
    Filed: July 7, 2021
    Publication date: December 1, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Ting Wu, Cheng-Tung Huang, Jen-Yu Wang, Yung-Ching Hsieh, Po-Chun Yang, Jian-Jhong Chen, Bo-Chang Li
  • Publication number: 20220371266
    Abstract: Provided are compositions that may be referred to as photoreactive compositions or inks. The compositions may have a plurality of reactive components, which are silica nanocages with one or more photoreactive ligand(s). Also provided are methods of making an article of manufacture. Also provided are articles of manufacture and uses thereof. The article of manufacture may be formed from a composition of the present disclosure.
    Type: Application
    Filed: November 2, 2020
    Publication date: November 24, 2022
    Inventors: Jen-Yu Huang, Tangi Aubert, Tobias Hanrath, Ulrich B. Wiesner
  • Publication number: 20220367390
    Abstract: A semiconductor device comprises a metallization layer, a passivation layer disposed above the metallization layer, a copper redistribution layer disposed on the passivation layer, a second passivation layer disposed on the copper redistribution layer, and a polyimide layer disposed over the second passivation layer. The polyimide layer and the second passivation layer include a continuous gap there-through that exposes a portion of the copper redistribution layer.
    Type: Application
    Filed: January 12, 2022
    Publication date: November 17, 2022
    Inventors: Cheng-Feng WU, Chih-Jen YU
  • Patent number: 11469201
    Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 11, 2022
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Wen-Sung Hsu, Ta-Jen Yu, Andrew C. Chang
  • Publication number: 20220310482
    Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 29, 2022
    Inventors: Sheng-Tsung Hsiao, Jen Yu Wang, Chung-Jung Wu, Tung-Liang Shao, Chih-Hang Tung
  • Publication number: 20220298277
    Abstract: A method for manufacturing a polymer emulsion includes the following steps. A mixture is heated to a first temperature less than or equal to about 40° C. The mixture including about 100 to about 500 parts by weight of a monomer and about 0.5 to about 95 parts by weight of a first cross-linking agent, in which the monomer has a structure of formula (I): and R1, R2, and R3 represent H or C1-C4 alkyl group, respectively. About 0.005 to about 5 parts by weight of a first initiator is added. About 0.003 to about 5 parts by weight of a reducing agent is added to form an intermediate product. The intermediate product is heated to a second temperature less than or equal to about 92° C.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 22, 2022
    Inventor: Jen-Yu LIU
  • Patent number: D976894
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: January 31, 2023
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Jen-Yu Chiang, Wang-Hung Yeh, Hsin-Chieh Fang, Shu-Hsien Chu