Patents by Inventor Jeng-Jye Shau

Jeng-Jye Shau has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Area efficient through-hole connections
    Patent number: 8709945
    Abstract: Using printing technologies to fill conductor materials into holes in silicon substrate, the preferred embodiments of the present improve cost efficiency of through-hole connections. Using silicon substrate as cathode terminal during electrical plating that fill holes in a silicon substrate with conductors, the preferred embodiments of the present improve alignment accuracy and cost efficiency of through-hole manufacturing processes.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: April 29, 2014
    Inventor: Jeng-Jye Shau
  • Area reduction for surface mount package chips
    Patent number: 8710645
    Abstract: Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: April 29, 2014
    Inventor: Jeng-Jye Shau
  • Area efficient through-hole connections
    Patent number: 8368228
    Abstract: Using developed photo-resist materials as insulator materials for through-hole connections, the preferred embodiments of the present invention improve the area efficiency of electrical devices manufactured on silicon substrates. The area efficiency is further improved by opening holes from both sides of silicon substrate to form through-holes. Besides area efficiency, these methods also provide better control in parasitic impedance of through-hole connection.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: February 5, 2013
    Inventor: Jeng-Jye Shau
  • Accurate alignment for stacked substrates
    Patent number: 8365398
    Abstract: Using developed photo-resist materials at the side walls of silicon substrates, the preferred embodiments of the present invention improve alignment accuracy of stacked substrates. Such alignment accuracy improves the area efficiency of side-wall connections as well as through-hole connections. The parasitic impedances of stacked substrate connections are also improved.
    Type: Grant
    Filed: April 10, 2011
    Date of Patent: February 5, 2013
    Inventor: Jeng-Jye Shau
  • POWER EFFICIENT DYNAMIC RANDOM ACCESS MEMORY DEVICES
    Publication number: 20120243299
    Abstract: The present invention provides methods and structures for improving refresh power efficiency of dynamic random access memory devices. By measuring charge retention properties of reference cells that have substantially the same structures as normal DRAM memory cells, the refresh rate of DRAM devices can be adjusted with better reliability. The reliability is further improved by using ECC circuits and/or field programmable redundancy circuits.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Inventor: Jeng-Jye Shau
  • ACCURATE ALIGNMENT FOR STACKED SUBSTRATES
    Publication number: 20120186078
    Abstract: Using developed photo-resist materials at the side walls of silicon substrates, the preferred embodiments of the present invention improve alignment accuracy of stacked substrates. Such alignment accuracy improves the area efficiency of side-wall connections as well as through-hole connections. The parasitic impedances of stacked substrate connections are also improved.
    Type: Application
    Filed: April 10, 2011
    Publication date: July 26, 2012
    Inventor: Jeng-Jye Shau
  • AREA EFFICIENT THROUGH-HOLE CONNECTIONS
    Publication number: 20120190193
    Abstract: Using printing technologies to fill conductor materials into holes in silicon substrate, the preferred embodiments of the present improve cost efficiency of through-hole connections. Using silicon substrate as cathode terminal during electrical plating that fill holes in a silicon substrate with conductors, the preferred embodiments of the present improve alignment accuracy and cost efficiency of through-hole manufacturing processes.
    Type: Application
    Filed: March 6, 2012
    Publication date: July 26, 2012
    Inventor: Jeng-Jye Shau
  • Ultra-low power hybrid circuits
    Patent number: 8164969
    Abstract: The present invention provides a solution to avoid the robustness problems of sub-threshold circuits by switching small parts of circuits to nominal-voltage only when they are being used, and switching them back to sub-threshold levels when the operation finishes. Such “hybrid sub-threshold” approach is capable of supporting ultra-low power operation without the disadvantages of sub-threshold circuits. Hybrid power saving mode for logic circuits provide significant power saving and fast recovery time without performance degradation.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: April 24, 2012
    Inventor: Jeng-Jye Shau
  • RANKING BY SIMILARITY LEVEL IN MEANING FOR WRITTEN DOCUMENTS
    Publication number: 20120095993
    Abstract: The present invention provides tools to help readers select among large number of written documents by ranking using similarity level in meaning. The ranking tools also can be combined with other ranking methods such as ranking in popularity or ranking by expert opinions. Potential applications include ranking of web pages, electrical mails, academic articles, patent publications, The Bible, or other written documents.
    Type: Application
    Filed: October 18, 2010
    Publication date: April 19, 2012
    Inventor: Jeng-Jye Shau
  • High Performance Output Drivers and Anti-Reflection Circuits
    Publication number: 20110133773
    Abstract: Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s).
    Type: Application
    Filed: April 30, 2010
    Publication date: June 9, 2011
    Applicant: UniRAM Technology Inc.
    Inventor: Jeng-Jye Shau
  • AREA REDUCTION FOR SURFACE MOUNT PACKAGE CHIPS
    Publication number: 20110133337
    Abstract: Using side-wall conductor leads deposited on the side-walls of a base substrate to form package level conductor leads for active circuits manufactured on silicon substrate(s) stacked on the base substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 9, 2011
    Inventor: Jeng-Jye Shau
  • HIGH PERFORMANCE LOW POWER OUTPUT DRIVERS
    Publication number: 20110133780
    Abstract: Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. In combination with RC termination circuits, output drivers of the present invention can be fully compatible with HSTL, SSTL, GTL, BTL, SATA, PCIe, LVDS, MIPI, MDDI or other partial voltage interfaces.
    Type: Application
    Filed: February 3, 2010
    Publication date: June 9, 2011
    Inventor: Jeng-Jye Shau
  • High Performance Low Power Output Drivers
    Publication number: 20110133772
    Abstract: Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. In combination with RC termination circuits, output drivers of the present invention can be fully compatible with HSTL, SSTL, GTL, BTL, SATA, PCIe, LVDS, MIPI, MDDI or other partial voltage interfaces.
    Type: Application
    Filed: December 4, 2009
    Publication date: June 9, 2011
    Applicant: UNIRAM TECHNOLOGY INC.
    Inventor: Jeng-Jye Shau
  • AREA EFFICIENT THROUGH-HOLE CONNECTIONS
    Publication number: 20110115097
    Abstract: Using developed photo-resist materials as insulator materials for through-hole connections, the preferred embodiments of the present invention improve the area efficiency of electrical devices manufactured on silicon substrates. The area efficiency is further improved by opening holes from both sides of silicon substrate to form through-holes. Besides area efficiency, these methods also provide better control in parasitic impedance of through-hole connection.
    Type: Application
    Filed: January 26, 2011
    Publication date: May 19, 2011
    Inventor: Jeng-Jye Shau
  • Area reduction for electrical diode chips
    Publication number: 20110089541
    Abstract: Using electrical printing technologies to form package level conductor leads for electrical diode circuit, the preferred embodiments of the present invention significantly reduces the areas of surface mount electrical diodes or ESD circuits. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. Additional cost reduction can be achieved by using none-crystalline semiconductor electrical diodes.
    Type: Application
    Filed: October 19, 2009
    Publication date: April 21, 2011
    Inventor: Jeng-Jye Shau
  • AREA REDUCTION FOR SURFACE MOUNT PACKAGE CHIPS
    Publication number: 20110089555
    Abstract: Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.
    Type: Application
    Filed: January 13, 2010
    Publication date: April 21, 2011
    Applicant: UNIRAM TECHNOLOGY INC.
    Inventor: Jeng-Jye Shau
  • Area reduction for die-scale surface mount package chips
    Publication number: 20110089557
    Abstract: Using side-wall conductor leads to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of die-scale surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.
    Type: Application
    Filed: December 11, 2009
    Publication date: April 21, 2011
    Inventor: Jeng-Jye Shau
  • Area reduction for electrical diode chips
    Publication number: 20110089542
    Abstract: Using electrical printing technologies to form package level conductor leads for electrical diode circuit, the preferred embodiments of the present invention significantly reduces the areas of surface mount electrical diodes or ESD circuits. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. Additional cost reduction can be achieved by using none-crystalline semiconductor electrical diodes.
    Type: Application
    Filed: November 25, 2009
    Publication date: April 21, 2011
    Inventor: Jeng-Jye Shau
  • Power saving termination circuits for dram modules
    Publication number: 20100327902
    Abstract: The present invention provides power saving methods by replacing termination resistors used to support SSTL DRAM interfaces with RC termination circuits; the RC termination circuits consumes significant less power relative to prior art termination resistors at low frequency and behave as a matching impedance at high frequency. Similar methods and structures are also applicable for PCIe, SATA, or MIPI differential interfaces.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 30, 2010
    Inventor: Jeng-Jye Shau
  • High Performance Output Drivers and Anti-Reflection Circuits
    Publication number: 20100237904
    Abstract: Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s).
    Type: Application
    Filed: June 7, 2010
    Publication date: September 23, 2010
    Applicant: UNIRAM TECHNOLOGY INC.
    Inventor: Jeng-Jye Shau