Abstract: The present invention provides novel power saving methods for programmable logic array (PLA) circuits. One method is to store the results of a previous PLA operation, and bypass a new operation if the inputs are the same as previous operation. Another method is to reset the PLA outputs when the correct results can be achieved by resetting output latches. A large PLA is divided into smaller sub-PLA's while individual sub-PLA's are controlled separately. It is therefore possible to save power by bypassing unrelated sub-PLA's. PLA's of the present invention consume less power than equivalent prior art PLA's by orders of magnitudes. For most cases, PLA's of the present invention also have better performance and better cost efficiency. The design procedures are completely controlled by user-friendly computer aid design tools. The regular structures of PLA and the simplicity in connections allow us to avoid RC effects of conductor lines.

Abstract: The present invention teaches novel electrically programmable read only memory (EPROM) devices for embedded applications. EPROM devices of the present invention utilize existing circuit elements without complicating existing manufacture technologies. They can be manufactured by dynamic random access memory (DRAM) technologies, standard logic technologies, or any type of IC manufacture technologies. Unlike conventional EPROM devices, these novel devices do not require high voltage circuits to support their programming operation. EPROM devices of the present invention are ideal for embedded applications. Typical applications including the redundancy circuits for DRAM, the programmable firmware for logic products, and the security identification circuits for IC products.

Abstract: This invention discloses a demodulation method. The method includes steps of: A) Receiving a modulated input signal having an input signal frequency. B) Generating a first switch control signal at a first switching frequency substantially equal to the input signal frequency. C) Generating a second switch control signal having the same frequency as the first switch control signal and having a phase that is approximately 90 degrees different from a phase of the first switch control signal. And D) Controlling at least two switching circuits with the first and second switch control signals for obtaining at least two sets of sampled amplitudes of the input signals for generating switching output signals for each of the switching circuits defined by subtracting the sampled amplitudes when the first switch control signal is high by the sampled amplitudes when the first switch control signal is low for each of the switching circuits to generate demodulated output signals for the modulated input signal.

Abstract: The present invention discloses novel methods to transfer data between a plurality of integrated circuit dice on a semiconductor wafer. Each individual die contains internal circuits to control data transfer to nearby dice. Wafer level data transfer is achieved by a series of inter-dice data transfers. It is therefore possible to use a small number of small area metal lines to support wafer level parallel processing activities. External connections are provided by a small number of bonding pads on each wafer. The load on each external bounding pad is by far lower than that of prior art wafer level connections. These inter-dice data transfer mechanism also can be programmed to avoid defective circuitry. This invention has been used to support wafer level functional tests and wafer level burn-in tests. A Testing system of the present invention can test thousands of dice in parallel using simple testing equipment. Testing costs for integrated circuits are therefore reduced dramatically.

Abstract: This invention discloses a method for changing a configuring ot an error correction code (ECC) logic circuit for performing an error-check of a changed data-width. The method includes the steps of: A) sequentially interconnecting a set of N1 identical error-check blocks where N1 is a first positive integer. And, the method further includes a step B) of reconfiguring the ECC logic circuit by changing the ECC logic circuit to a set of N2 sequentially interconnected circuits comprising N2 of the identical error-check blocks where N2 is a second positive number. In a preferred embodiment, the step of sequentially interconnecting a set of N1 identical error-check blocks is a step of interconnecting the N1 error-check blocks only between sequentially neighboring blocks for transmitting signals only between the neighboring error-check blocks.

Abstract: This invention provides practical methods to make a DRAM fully compatible with existing SRAM products. This is accomplished by design and manufacture methods according to the invention, which includes a method to reduce standby power of reference voltage generators and a method to avoid the alpha particle problem using a novel error correction code (ECC) mechanism. The reference voltage generator of the present invention can adjust the values of output voltage and driving power separately following simple procedures. It has very strong driving power to maintain the reference voltage, which is necessary to support high- speed operation of memory devices of the present invention. In the mean time, its standby power can be reduced by orders of magnitudes using simple control mechanism, which is necessary to make our memory device compatible with the properties of existing SRAM products. There is no need to use feedback circuits or operation amplifiers, so the circuit is extremely stable and reliable.

Abstract: A semiconductor memory array comprises a plurality of memory cells wherein each memory cell further includes a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells. The memory array further includes a memory cell read/write voltage control circuit for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V0 and second voltage V1 wherein Vdd>V1>V0>Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array. The memory array further includes a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second word-lines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage.

Abstract: The present invention discloses novel methods to transfer data between a plurality of integrated circuit dice on a semiconductor wafer. Each individual die contains internal circuits to control data transfer to nearby dice. Wafer level data transfer is achieved by a series of inter-dice data transfers. It is therefore possible to use a small number of small area metal lines to support wafer level parallel processing activities. External connections are provided by a small number of bonding pads on each wafer. The load on each external bounding pad is by far lower than that of prior art wafer level connections. These inter-dice data transfer mechanism also can be programmed to avoid defective circuitry. This invention has been used to support wafer level functional tests and wafer level burn-in tests. A Testing system of the present invention can test thousands of dice in parallel using simple testing equipment. Testing costs for integrated circuits are therefore reduced dramatically.

Abstract: A semiconductor memory array comprising a plurality of memory cells wherein each memory cell further includes a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells. The memory array further includes a memory cell read/write voltage control circuit for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V0 and second voltage V1 wherein Vdd>V1>V0>Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array. The memory array further includes a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second wordlines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage.

Abstract: The present invention provides novel power saving methods for programmable logic array (PLA) circuits. One method is to store the results of a previous PLA operation, and bypass a new operation if the inputs are the same as previous operation. Another method is to reset the PLA outputs when the correct results can be achieved by resetting output latches. A large PLA is divided into smaller sub-PLA's while individual sub-PLA's are controlled separately. It is therefore possible to save power by bypassing unrelated sub-PLA's. PLA's of the present invention consume less power than equivalent prior art PLA's by orders of magnitudes. For most cases, PLA's of the present invention also have better performance and better cost efficiency. The design procedures are completely controlled by user-friendly computer aid design tools. The regular structures of PLA and the simplicity in connections allow us to avoid RC effects of conductor lines.

Abstract: The present invention provides novel electrically programmable read only memory (EPROM) devices for embedded applications. EPROM devices of the present invention utilize existing circuit elements without complicating existing manufacture technologies. The novel EPROM device can be manufactured by applying the manufacturing processes used for making dynamic random access memory (DRAM), standard logic technologies or any type of IC manufacture technologies. Unlike conventional EPROM devices, these novel devices do not require high voltage circuits to support their programming operation. The EPROM devices of the present invention are ideal for embedded applications. Typical applications including the redundancy circuits for the programmable firmware for logic products, and the security identification circuits for IC products.

Abstract: A semiconductor erasable programmable read-only memory (EPROM) device provided for operation with a plurality of first level sense-circuits. The EPROM memory device includes an EPROM memory cell array having a plurality of first-direction first-level bit lines disposed in a parallel manner along a first direction. The EPROM memory device further includes a plurality of word lines intersected with the first-direction first-level bit lines. The EPROM memory cell array further includes a plurality of EPROM memory cells wherein each of the plurality of memory cells being coupled between one of the first-direction first level bit lines and one of the word lines for storing data therein. And, the EPROM memory device further includes a plurality of different-direction first level bit-lines disposed along at least one different direction different from the first direction.

Abstract: A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

Abstract: The present invention provides cost saving integrated circuit (IC) design methods pre-defined masks. The same front-end structures are used not only by core circuits but also by peripheral structures including input/output (I/O) devices, bonding pads, seal rings, and scribe lanes. These methods allow high utilization rates for a wide variety of products. Additional cost saving is achieved by separately manufacturing I/O circuits and bonding pads using low cost IC technologies. Testing methods and special inter-module connection methods are provided to support IC modules that do not have connections to external pins.

Abstract: The present invention provides novel power saving methods for programmable logic array (PLA) circuits. One method is to store the results of a previous PLA operation, and bypass a new operation if the inputs are the same as previous operation. Another method is to reset the PLA outputs when the correct results can be achieved by resetting output latches. A large PLA is divided into smaller sub-PLA's while individual sub-PLA's are controlled separately. It is therefore possible to save power by bypassing unrelated sub-PLA's. PLA's of the present invention consume less power than equivalent prior art PLA's by orders of magnitudes. For most cases, PLA's of the present invention also have better performance and better cost efficiency. The design procedures are completely controlled by user-friendly computer aid design tools. The regular structures of PLA and the simplicity in connections allow us to avoid RC effects of conductor lines.

Abstract: A semiconductor memory array comprising a plurality of memory cells wherein each memory cell further includes a first and a second bit-lines and a first and a second word-lines connected to each of the memory cells. The memory array further includes a memory cell read/write voltage control circuit for controlling each of the first and second bit-lines to have a bitline voltage higher, lower and within a medium voltage range between a first voltage V0 and second voltage V1 wherein Vdd>V1>V0>Vgnd where Vdd is a power supply voltage, and Vgnd is a ground voltage for the memory array. The memory array further includes a first read/write port and a second read/write port for independently carrying out a read/write operation by activating the first and second word-lines respectively and by controlling the first and second bit-lines respectively to have a bit-line voltage higher, lower or within the medium voltage range between the first and the second voltage.

Abstract: A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

Abstract: This invention provides practical methods to make a DRAM fully compatible with existing SRAM products. This is accomplished by design and manufacture methods according to the invention, which includes a method to reduce standby power of reference voltage generators and a method to avoid the alpha particle problem using a novel error correction code (ECC) mechanism. The reference voltage generator of the present invention can adjust the values of output voltage and driving power separately following simple procedures. It has very strong driving power to maintain the reference voltage, which is necessary to support high-speed operation of memory devices of the present invention. In the mean time, its standby power can be reduced by orders of magnitudes using simple control mechanism, which is necessary to make our memory device compatible with the properties of existing SRAM products. There is no need to use feedback circuits or operation amplifiers, so the circuit is extremely stable and reliable.

Abstract: A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

Abstract: An analog signal processing circuit is disclosed in this invention. The analog signal processes performed by the circuit of this invention involve mathematical operations of summation, subtraction, multiplication, division, automatic control and different types of filtering operations. Furthermore, a plurality of single-stage circuits may be interconnected to carry out combination of analog signal processing functions according to the methods and circuit configuration provided in this invention. The analog signal processing processes are performed by the analog signal processing circuit through the balance of currents by combining the basic circuit elements of current mirrors, voltage control signal amplifiers, and current sources and sinks. The circuits developed for carrying out these analog signal-processing steps can also be implemented for optical location tracking systems.