Abstract: A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

Abstract: The present invention discloses novel methods to transfer data between a plurality of integrated circuit blocks on a semiconductor wafer. Each individual circuit blocks contains internal circuits to control data transfer to nearby circuit blocks. Long distance signal transfer is achieved by a series of short distance data transfers. Such signal transfer methods provide many possible paths to transfer data between two points, allowing the possibility to bypass defective circuits. The present invention allows the possibility to integrate large amount of circuits into a single IC product while achieving excellent yield.

Abstract: The present invention provides methods to arrange non-volatile memory transistor array by rotating the word line and bit line directions 90 degrees relative to that of prior art NOR FLASH devices. These methods effectively reduce the areas of non-volatile memory devices. Additional changes in control mechanism are required to support the operations of such non-volatile memory devices.

Abstract: Data transfer system of the present invention examines existing communication methods for unused bandwidth. Data signals are inserted into communication signal when unused bandwidth is found. The resulting signal is still used for prior art communication without sacrificing quality. These data transfer methods provide an alternative high-bandwidth data path to Internet. It will satisfy the bandwidth requirement for many applications without any changes to existing system. The system requires little resource to implement. It is the most cost efficient method to solve the bandwidth problem, and the system can be established in a short time.

Abstract: The present invention uses mechanical sound waves as sound waves as signal carriers for establishing wireless connections for wide varieties of devices. Example applications include computer mice, computer keyboard, video game controller, wireless telephone, cellular phone, household appliance control, ID device, and security system.

Abstract: Data transfer system of the present invention examines TV video signal for unused bandwidth. Data signals are inserted into TV video signal when unused bandwidth is found. The resulting video signal is still used for TV display without sacrificing video quality. These data transfer methods provide an alternative high-bandwidth data path to Internet. It will satisfy the bandwidth requirement for many applications without any changes to existing system. The system requires little resource to implement. It is the most cost efficient method to solve the bandwidth problem, and the system can be established in a short time.

Abstract: The present invention provides novel power saving methods for programmable logic array (PLA) circuits that includes diodes. One method is to store the results of a previous PLA operation, and bypass a new operation if the inputs are the same as previous operation. Another method is to reset the PLA outputs when the correct results can be achieved by resetting output latches. A large PLA is divided into smaller sub-PLA's while individual sub-PLA's are controlled separately. It is therefore possible to save power by bypassing unrelated sub-PLA's. PLA's of the present invention consume less power than equivalent prior art PLA's by orders of magnitudes. For most cases, PLA's of the present invention also have better performance and better cost efficiency. The design procedures are completely controlled by user-friendly computer aid design tools. The regular structures of PLA and the simplicity in connections allow us to avoid RC effects of conductor lines.

Abstract: The present invention utilizes voltage coupling effects of MOS capacitors to support logic operations for integrated circuits such as programmable logic array, optical sensors, comparators, and storage devices. Additional flexibility is achieved by using the voltage coupling effects of floating gate capacitors to support applications such as field programmable logic and non-volatile memory devices. Integrated circuits of the present invention occupy much smaller areas comparing to equivalent prior art integrated circuits, achieving dramatic cost reduction. Further cost reduction can be achieved by fabricating coupling circuits of the present invention on low quality substrates as 3 dimensional devices. The major drawback of the present invention is smaller signal to noise ratio, which is overcome by proper voltage control and sensing circuits. Special considerations to support hot carrier programming and current mode reading are also disclosed in this patent.

Abstract: High performance memory devices have been realized by applying an Evenly Scaled Multiple Level Architecture (ESMLA) using block select arrangement. A single-bit-line-write mechanism allows us to reduce the number of bit lines by 50% for static memory devices. The resulting memory device can be as fast as registers files while its area is smaller than prior art high-density memory devices. The scaling method of the memory architecture also assures that the speed of the memory devices will scale in the same rate as logic circuits in future IC manufacture technologies.

Abstract: The present invention discloses novel methods to transfer data between a plurality of integrated circuit dice on a semiconductor wafer. Each individual die contains internal circuits to control data transfer to nearby dice. Wafer level data transfer is achieved by a series of inter-dice data transfers. It is therefore possible to use a small number of small area metal lines to support wafer level parallel processing activities. External connections are provided by a small number of bonding pads on each wafer. The load on each external bounding pad is by far lower than that of prior art wafer level connections. These inter-dice data transfer mechanism also can be programmed to avoid defective circuitry. This invention has been used to support wafer level functional tests and wafer level burn-in tests. A Testing system of the present invention can test thousands of dice in parallel using simple testing equipment. Testing costs for integrated circuits are therefore reduced dramatically.

Abstract: A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

Abstract: An electronic device supported on a semiconductor substrate. The semiconductor device includes a diffusion area in the substrate and a polysilicon layer extending over the substrate and contacting the diffusion area. The electronic device further includes a conductive contact covering and contacting both the polysilicon layer and the diffusion area. Therefore, the semiconductor device disclosed in this invention includes poly-to-diffusion connection for a semiconductor device that has a diffusion are and a polysilicon area. The semiconductor device further includes a contact that covers both the diffusion area and the polysilicon area with a contact filling material forming the connection between these two areas.

Abstract: A dynamic random access memory solves long-existing tight pitch layout problems using a multiple-dimensional bit line structure. Improvement in decoder design further reduces total area of this memory. A novel memory access procedure provides the capability to make internal memory refresh completely invisible to external users. By use of such memory architecture, higher performance DRAM can be realized without degrading memory density. The requirements for system support are also simplified significantly.

Abstract: The present invention teaches novel electrically programmable read only memory (EPROM) devices for embedded applications. EPROM devices of the present invention utilize existing circuit elements without complicating existing manufacture technologies. They can be manufactured by dynamic random access memory (DRAM) technologies, standard logic technologies, or any type of IC manufacture technologies. Unlike conventional EPROM devices, these novel devices do not require high voltage circuits to support their programming operation. EPROM devices of the present invention are ideal for embedded applications. Typical applications including the redundancy circuits for DRAM, the programmable firmware for logic products, and the security identification circuits for IC products.

Abstract: This invention provides practical methods to fabricate sub-micron 3D integrated circuits using multiple layers of diodes manufactured on polycrystalline or amorphous semiconductor thin films. The long existing problems for using poly diodes for high density IC are solved by design and manufacture methods. The circuit design methods of the present invention improve the tolerance in non-ideal properties of diodes. The resulting IC products can function correctly even when many of their diodes are defective. We also developed manufacture procedures fully compatible with current art IC technologies. No additional masking steps or high temperature procedures are used. The 3D IC devices of the present invention are ready to be manufactured by current art IC technologies. Integrated circuits with unprecedented densities are therefore realized by stacking thin film diodes upon common active devices.

Abstract: High performance memory devices have been realized by applying an Evenly Scaled Multiple Level Architecture (ESMLA) using block select arrangement. A single-bit-line-write mechanism allows us to reduce the number of bit lines by 50% for static memory devices. The resulting memory device can be as fast as registers files while its area is smaller than prior art high-density memory devices. The scaling method of the memory architecture also assures that the speed of the memory devices will scale in the same rate as logic circuits in future IC manufacture technologies.

Abstract: A demodulator for demodulating a modulated input signal transmitted at a carrier frequency includes a current mirror for receiving the modulated input signal and generating a first and a second current-mirror output signals of same amplitude and frequency as the modulated input signal. The demodulator further includes a first and a second switch-controlled sampling circuits connected to the current mirror for receiving the first and second current mirror output signals respectively. The demodulator further includes a switching signal generator provided for generating a first and a second switch control signals having a frequency substantially equals to the carrier frequency with a flexibly adjustable phase difference between the first and the second switch control signals.

Abstract: Integrated circuit (IC) manufacture procedures are developed to reduce connected diffusion areas. Using a diffusion connection layer that is deposited immediately on exposed diffusion areas, high quality electrical connection is achieved while avoiding critical contact design rules. The resulting procedure provides 20%-40% area reduction for most of integrated circuits. Significant improvements in power and performance also can be achieved.

Abstract: Using 6 transistor memory cell to replace prior art 10 transistor binary content addressable memory (CAM) cells, and using 10 transistor ternary CAM (TCAM) cell to replace prior art 16 transistor TCAM cells, the present invention provided significant cost saving for high density CAM products. The power consumption problems of prior art high density CAM devices are solved by novel zoned lookup mechanism. For a high density CAM storing sorted data, lookup mechanisms of the present invention can reduce power consumption by two orders of magnitudes.

Abstract: The present invention teaches novel electrically programmable read only memory (EPROM) devices for embedded applications. EPROM devices of the present invention utilize existing circuit elements without complicating existing manufacture technologies. They can be manufactured by dynamic random access memory (DRAM) technologies, standard logic technologies, or any type of IC manufacture technologies. Unlike conventional EPROM devices, these novel devices do not require high voltage circuits to support their programming operation. EPROM devices of the present invention are ideal for embedded applications. Typical applications including the redundancy circuits for DRAM, the programmable firmware for logic products, and the security identification circuits for IC products.