Abstract: A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.

Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

Abstract: A semiconductor device includes a first semiconductor fin extending from a substrate, a first dielectric fin extending from the substrate adjacent a first side of the first semiconductor fin and a second dielectric fin extending from the substrate adjacent a second side of the first semiconductor fin, a first gate stack over and along sidewalls of the first semiconductor fin, the first dielectric fin, and the second dielectric fin, a first epitaxial source/drain region in the first semiconductor fin and extending from the first dielectric fin to the second dielectric fin, and an air gap between the first epitaxial source/drain region and the substrate, the air gap extending between the first dielectric fin and the second dielectric fin.

Abstract: A blood conduit with stent has a flexible conduit body and an expandable stent structure. The conduit body has a first opening end through which only an inflow of a blood enters and a second opening end through which only an outflow of the blood leaves. The stent structure includes a plurality of threads adhered to the conduit body and expands in directions intersecting an axial direction of the conduit body. A boundary of one of the threads of the stent structure closest to the second opening end is away from the second opening end with a predetermined distance, thereby preventing blood back flow into the false lumen via a new tear.

Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. The semiconductor feature comprises two lower portions and one upper portion. The two lower portions are directly over the two semiconductor fins respectively. The upper portion is over the two lower portions. A bottom surface of the upper portion has an arc-like cross-sectional shape.

Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

Abstract: A display device is provided to have an emission spectrum. The emission spectrum is performed in a white image of highest grey level and includes a first sub emission spectrum ranging from 380 nm to 478 nm and a second sub emission spectrum ranging from 479 nm to 780 nm, and the first sub emission spectrum has a maximum peak wavelength greater than or equal to 453 nm. An integral value of the first sub emission spectrum multiplied by a blue light hazard weighting function from 380 nm to 478 nm is defined as a first integration, and an integral value of the second sub emission spectrum multiplied by an eye function from 479 nm to 780 nm is defined as a second integration. A ratio of the first integration to the second integration is in a range from 40% to 65%.

Abstract: A memory device includes a semiconductor substrate having spaced apart source and drain regions, with a channel region of the substrate extending there between, a floating gate of polysilicon disposed over and insulated from a first portion of the channel region by insulation material having a first thickness, wherein the floating gate has a sloping upper surface that terminates in a sharp edge, a word line gate of polysilicon disposed over and insulated from a second portion of the channel region by insulation material having a second thickness, and an erase gate of polysilicon disposed over and insulated from the source region by insulation material having a third thickness, wherein the erase gate includes a notch that wraps around and is insulated from the sharp edge of the floating gate. The third thickness is greater than the first thickness, and the first thickness is greater than the second thickness.

Abstract: A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.

Abstract: The inventors have unexpectedly discovered that shock and/or potential multi-organ failure due to shock can be effectively treated by administration of liquid high-dose protease inhibitor formulations to a location upstream of where pancreatic proteases are introduced into the gastrointestinal tract. Most preferably, administration is directly to the stomach, for example, via nasogastric tube under a protocol effective to treat shock by such administration without the need of providing significant quantities of the protease inhibitor to the jejunum and/or ileum.

Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.

Abstract: A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.

Abstract: A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. The semiconductor feature comprises two lower portions and one upper portion. The two lower portions are directly over the two semiconductor fins respectively. The upper portion is over the two lower portions. A bottom surface of the upper portion has an arc-like cross-sectional shape.

Abstract: The inventors have unexpectedly discovered that shock and/or potential multi-organ failure due to shock can be effectively treated by administration of liquid high-dose protease inhibitor formulations to a location upstream of where pancreatic proteases are introduced into the gastrointestinal tract. Most preferably, administration is directly to the stomach, for example, via nasogastric tube under a protocol effective to treat shock by such administration without the need of providing significant quantities of the protease inhibitor to the jejunum and/or ileum.

Abstract: A method of forming a non-volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.

Abstract: A light source for a display device, includes: a first LED chip emitting a first light having a peak located within the range of wavelengths 380 nm to 500 nm, and a second LED chip emitting a second light having a peak located within the range of wavelengths 380 nm to 500 nm, wherein the peak wavelength of the second light is longer than the peak wavelength of the first light, and the difference between the peak wavelength of the second light and the peak wavelength of the first light is less than 40 nm and greater than or equal to 10 nm.

Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate, two semiconductor fins over the substrate, and a semiconductor feature over the two semiconductor fins. The semiconductor feature comprises two lower portions and one upper portion. The two lower portions are directly over the two semiconductor fins respectively. The upper portion is over the two lower portions. A bottom surface of the upper portion has an arc-like cross-sectional shape.

Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.