Abstract: A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

Abstract: A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an HKMG layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates.

Abstract: A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an HKMG layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates.

Abstract: A display apparatus comprises a display panel. The display panel emits a green light having a green energy and a green point of the CIE 1931 xy chromaticity under the operation of the highest gray level of a green image, and emits a blue light having a blue energy and a blue point of the CIE 1931 xy chromaticity under the operation of the highest gray level of a blue image. The ratio of the green energy to the blue energy is between 0.7 and 1.2. In the CIE 1931 chromaticity diagram, the coordinates of the blue point are bounded by the equation: y=?168.72x2+50.312x?3.635 and the equation: y=?168.72x2+63.81x?5.9174, while y is between 0.04 and 0.08.

Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

Abstract: A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.

Abstract: A liquid crystal display apparatus includes a display panel and a backlight module. The display panel includes a color filter layer having a blue filter portion. The backlight module emits light to the display panel. A peak wavelength of a blue light portion of the spectrum of the light is greater than or equal to 440 nm and smaller than or equal to 450 nm. The blue filter portion has a transmission spectrum having a first wavelength ?1 and a second wavelength ?2, and the first wavelength ?1 and the second wavelength ?2 conform to the following equation: 514 ? ? 1 2 + ? 2 2 + 0.71862 ? ? ? 2 - 0.71862 ? ? ? 1 ? 541 The first wavelength ?1 and the second wavelength ?2 are corresponding to a half level of a peak value of the transmission spectrum, and the unit thereof is nm.

Abstract: A memory device including a silicon semiconductor substrate, spaced apart source and drain regions formed in the substrate with a channel region there between, and a conductive floating gate disposed over a first portion of the channel region and a first portion of the source region. An erase gate includes a first portion that is laterally adjacent to the floating gate and over the source region, and a second portion that extends up and over the floating gate. A conductive word line gate is disposed over a second portion of the channel region. The word line gate is disposed laterally adjacent to the floating gate and includes no portion disposed over the floating gate. The thickness of insulation separating the word line gate from the second portion of the channel region is less than that of insulation separating the floating gate from the erase gate.

Abstract: A light source for a display device, includes: a first LED chip emitting a first light having a peak located within the range of wavelengths 380 nm to 500 nm, and a second LED chip emitting a second light having a peak located within the range of wavelengths 380 nm to 500 nm, wherein the peak wavelength of the second light is longer than the peak wavelength of the first light, and the difference between the peak wavelength of the second light and the peak wavelength of the first light is less than 40 nm and greater than or equal to 10 nm.

Abstract: The inventors have unexpectedly discovered that shock and/or potential multi-organ failure due to shock can be effectively treated by administration of liquid high-dose protease inhibitor formulations to a location upstream of where pancreatic proteases are introduced into the gastrointestinal tract. Most preferably, administration is directly to the stomach, for example, via nasogastric tube under a protocol effective to treat shock by such administration without the need of providing significant quantities of the protease inhibitor to the jejunum and/or ileum.

Abstract: A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.

Abstract: A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type.

Abstract: A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.

Abstract: A memory device and method including a semiconductor substrate with memory and logic device areas. A plurality of memory cells are formed in the memory area, each including first source and drain regions with a first channel region therebetween, a floating gate disposed over a first portion of the first channel region, a control gate disposed over the floating gate, a select gate disposed over a second portion of the first channel region, and an erase gate disposed over the source region. A plurality of logic devices formed in the logic device area, each including second source and drain regions with a second channel region therebetween, and a logic gate disposed over the second channel region. The substrate upper surface is recessed lower in the memory area than in the logic device area, so that the taller memory cells have an upper height similar to that of the logic devices.

Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.

Abstract: A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.

Abstract: A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

Abstract: A non-volatile memory cell includes a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over a second portion of the channel region adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.

Abstract: A non-volatile memory cell includes a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over a second portion of the channel region adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.

Abstract: A display module includes a light source and a display unit. The light source has an emission spectrum having maximum peak values corresponding to a first maximum peak wavelength and a second maximum peak wavelength. The display unit includes a green filter layer having a transmittance spectrum. The emission spectrum and the transmittance spectrum have a right cross-point and a left cross-point. A product of an emission intensity value of the emission spectrum corresponding to the right cross-point and a transmittance intensity value of the transmittance spectrum corresponding to the right cross-point is a first product value. A product of an emission intensity value of the emission spectrum corresponding to the left cross-point and a transmittance intensity value of the transmittance spectrum corresponding to the left cross-point is a second product value. A ratio of the first product value to the second product value is less than 20%.