Patents by Inventor Jenn-Hwa Huang
Jenn-Hwa Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170141190Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.Type: ApplicationFiled: February 1, 2017Publication date: May 18, 2017Inventors: Jenn Hwa Huang, Weixiao Huang
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Patent number: 9647075Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.Type: GrantFiled: September 16, 2015Date of Patent: May 9, 2017Assignee: NXP USA, INC.Inventors: Jenn Hwa Huang, Tianwei Sun, James A. Teplik
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Patent number: 9601638Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.Type: GrantFiled: October 19, 2011Date of Patent: March 21, 2017Assignee: NXP USA, INC.Inventors: Jenn Hwa Huang, Weixiao Huang
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Publication number: 20170077245Abstract: A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer is formed over the transistor, and a plurality of vias are electrically connected to the source structure. A metal layer is formed over the dielectric layer. The metal layer includes a field plate over the gate structure, a plurality of contact pads over each via, and a plurality of fingers interconnecting each one of the plurality of contact pads to the field plate.Type: ApplicationFiled: September 16, 2015Publication date: March 16, 2017Inventors: Jenn Hwa Huang, Tianwei Sun, James A. Teplik
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Publication number: 20160343809Abstract: An embodiment of a device includes a semiconductor substrate, a transistor formed at the first substrate surface, a first conductive feature formed over the first substrate surface and electrically coupled to the transistor, and a second conductive feature covering only a portion of the second substrate surface to define a first conductor-less region. A cavity vertically aligned with the first conductive feature within the first conductor-less region extends into the semiconductor substrate. A dielectric medium may be disposed within the cavity and have a dielectric constant less than a dielectric constant of the semiconductor substrate. A method for forming the device may include forming a semiconductor substrate, forming a transistor on the semiconductor substrate, forming the first conductive feature, forming the second conductive feature, forming the conductor-less region, forming the cavity, and filling the cavity with the dielectric medium.Type: ApplicationFiled: May 22, 2015Publication date: November 24, 2016Inventors: BRUCE M. GREEN, JENN HWA HUANG, VIKAS S. SHILIMKAR
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Publication number: 20160343833Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.Type: ApplicationFiled: August 1, 2016Publication date: November 24, 2016Inventors: Jenn Hwa Huang, James A. Teplik
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Patent number: 9425267Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.Type: GrantFiled: March 14, 2013Date of Patent: August 23, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Jenn Hwa Huang, James A. Teplik
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Publication number: 20150357452Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
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Patent number: 9153448Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.Type: GrantFiled: January 21, 2015Date of Patent: October 6, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
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Patent number: 9111868Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.Type: GrantFiled: June 26, 2012Date of Patent: August 18, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
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Publication number: 20150132932Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.Type: ApplicationFiled: January 21, 2015Publication date: May 14, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
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Patent number: 8946776Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.Type: GrantFiled: June 26, 2012Date of Patent: February 3, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
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Publication number: 20140264360Abstract: Transistors and methods of fabricating are described herein. These transistors include a field plate (108) and a charged dielectric layer (106) overlapping at least a portion of a gate electrode (102). The field plate (108) and charged dielectric layer (106) provide the ability to modulate the electric field or capacitance in the transistor. For example, the charged dielectric layer (106) provides the ability to control the capacitance between the gate electrode (102) and field plate (108). Modulating such capacitances or the electric field in transistors can facilitate improved performance. For example, controlling gate electrode (102) to field plate (108) capacitance can be used to improve device linearity and/or breakdown voltage. Such control over gate electrode (102) to field plate (108) capacitance or electric fields provides for high speed and/or high voltage transistor operation.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEXASInventors: Jenn Hwa HUANG, James A. TEPLIK
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Patent number: 8836133Abstract: An electronic apparatus includes a semiconductor substrate, a device structure supported by the semiconductor substrate, and a guard ring surrounding the device structure. The guard ring includes a plurality of conductive structures spaced apart from one another, supported by the semiconductor substrate, and coupled to a voltage source to establish an operating voltage for the guard ring.Type: GrantFiled: October 12, 2012Date of Patent: September 16, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Jenn Hwa Huang, Jose L. Suarez, Yun Wei
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Publication number: 20140103532Abstract: An electronic apparatus includes a semiconductor substrate, a device structure supported by the semiconductor substrate, and a guard ring surrounding the device structure. The guard ring includes a plurality of conductive structures spaced apart from one another, supported by the semiconductor substrate, and coupled to a voltage source to establish an operating voltage for the guard ring.Type: ApplicationFiled: October 12, 2012Publication date: April 17, 2014Inventors: Jenn Hwa Huang, Jose L. Suarez, Yun Wei
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Patent number: 8653558Abstract: In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.Type: GrantFiled: October 14, 2011Date of Patent: February 18, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Jenn Hwa Huang, Weixiao Huang
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Publication number: 20130341679Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.Type: ApplicationFiled: June 26, 2012Publication date: December 26, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
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Publication number: 20130341678Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.Type: ApplicationFiled: June 26, 2012Publication date: December 26, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
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Publication number: 20130099324Abstract: A low leakage current switch device (110) is provided which includes a GaN-on-Si substrate (11, 13) with one or more device mesas (41) in which isolation regions (92, 93) are formed using an implant mask (81) to implant ions (91) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode (111) from contacting the peripheral edge and sidewalls of the mesa structures.Type: ApplicationFiled: October 19, 2011Publication date: April 25, 2013Inventors: Jenn Hwa Huang, Weixiao Huang
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Publication number: 20130092947Abstract: In some embodiments, a metal insulator semiconductor heterostructure field effect transistor (MISHFET) is disclosed that has a source, a drain, an insulation layer, a gate dielectric, and a gate. The source and drain are on opposing sides of a channel region of a channel layer. The channel region is an upper portion of the channel layer. The channel layer comprises gallium nitride. The insulation layer is over the channel layer and has a first portion and a second portion. The first portion is nearer the drain than the source and has a first thickness. The second portion is nearer the source than drain and has the first thickness. The insulation layer has an opening through the insulation layer. The opening is between the first portion and the second portion.Type: ApplicationFiled: October 14, 2011Publication date: April 18, 2013Inventors: BRUCE M. GREEN, Jenn Hwa Huang, Weixiao Huang