Abstract: A Schottky gate (27?, 27?) of a metal-semiconductor FET (20?, 20?) is formed on a semiconductor comprising substrate (21) by, etching a gate recess (36) so as to expose a slightly depressed surface (362) of the substrate (21), the etching step also producing surface undercut cavities (363) extending laterally under the etch mask (43) from the gate recess (36), then conformally coating the slightly depressed surface (362) with a first Schottky forming conductor (40?) and substantially also coating inner surfaces (366) of the surface undercut cavities (363), and forming a Schottky contact to the semiconductor comprising substrate (21), adapted when biased to control current flow in a channel (22) extending between source (23) and drain (24) of the FET (20?, 20?) under the gate recess (36).

Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.

Abstract: A multimodal integrated circuit (IC) is provided, comprising, first (74) and second (76) semiconductor (SC) devices, and first (78) and second (80) integrated passive devices (IPDs) coupled, respectively, to the first (74) and second (76) SC devices, wherein the first IPD (78) overlies the second SC device (76) and the second IPD (80) overlies the first SC device (74) chosen such that the underlying SC device (74, 76) is not active at the same time as its overlying IPD (80, 78). By placing the IPDs (78, 80) over the SC devices (76, 74) a compact IC layout is obtained. Since the overlying IPD (78, 80) and underlying SC (76, 74) are not active at the same time, undesirable cross-talk (68, 69) between the IPDs (78, 80) and the SC devices (76, 74) is avoided. This arrangement applies to any IC having multiple signal paths (RF1, RF2) where the IPDs (78, 80) of a first path (RF1, RF2) may be placed over the SC devices (76, 74) of a second path (RF2, RF1) not active at the same time.

Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.

Abstract: A Schottky gate (27?, 27?) of a metal-semiconductor FET (20?, 20?) is formed on a semiconductor comprising substrate (21) by, etching a gate recess (36) so as to expose a slightly depressed surface (362) of the substrate (21), the etching step also producing surface undercut cavities (363) extending laterally under the etch mask (43) from the gate recess (36), then conformally coating the slightly depressed surface (362) with a first Schottky forming conductor (40?) and substantially also coating inner surfaces (366) of the surface undercut cavities (363), and forming a Schottky contact to the semiconductor comprising substrate (21), adapted when biased to control current flow in a channel (22) extending between source (23) and drain (24) of the FET (20?, 20?) under the gate recess (36).

Abstract: A multimodal integrated circuit (IC) is provided, comprising, first (74) and second (76) semiconductor (SC) devices, and first (78) and second (80) integrated passive devices (IPDs) coupled, respectively, to the first (74) and second (76) SC devices, wherein the first IPD (78) overlies the second SC device (76) and the second IPD (80) overlies the first SC device (74) chosen such that the underlying SC device (74, 76) is not active at the same time as its overlying IPD (80, 78). By placing the IPDs (78, 80) over the SC devices (76, 74) a compact IC layout is obtained. Since the overlying IPD (78, 80) and underlying SC (76, 74) are not active at the same time, undesirable cross-talk (68, 69) between the IPDs (78, 80) and the SC devices (76, 74) is avoided. This arrangement applies to any IC having multiple signal paths (RF1, RF2) where the IPDs (78, 80) of a first path (RF1, RF2) may be placed over the SC devices (76, 74) of a second path (RF2, RF1) not active at the same time.

Abstract: A micro-electro-mechanical device (10) including a shorting bar (40) having a first portion (42) electrically coupled to a first input/output signal line (34) and a second portion (43) electrically uncoupled to a second input/output signal line (36). Shorting bar (40) is coupled to a moveable end (49) of a cantilever structure (44). Thus, preferably only the second portion (43) of shorting bar (40) needs to be actuated to be electrically coupled to the second input/output signal line (36).

Abstract: A micro-electro-mechanical device (10) including a shorting bar (40) having a first portion (42) electrically coupled to a first input/output signal line (34) and a second portion (43) electrically uncoupled to a second input/output signal line (36). Shorting bar (40) is coupled to a moveable end (49) of a cantilever structure (44). Thus, preferably only the second portion (43) of shorting bar (40) needs to be actuated to be electrically coupled to the second input/output signal line (36).

Abstract: A series of switchable and tunable filters is provided. The filters are manufactured using coplanar waveguide fabrication techniques and micro-electro-mechanical (MEM) system switches. By making a MEM switch conductive to connect two portions of a filter element, a filter inductor is implemented. By making the MEM switch non-conductive, a filter capacitor is implemented. This results in smaller filters that can be either switched between a band pass filter and a low pass filter or switched between operating ranges.

Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

Abstract: A microelectromechanical system (MEMS) switch assembly (10) and a method of forming the MEMBS switch assembly (10) is provided that includes a switching member (12) having a first portion (34) that is at least partially formed with a first material having a first dielectric constant and a second portion (36) that is at least partially formed with a second material having a second dielectric constant. Furthermore, the switching member (12) further includes a first lead (14) spaced apart from a second lead (16) for contacting the switching member (12). In operation, the switching member (12) is configured for movement such that the first portion (34) and second portion (36) of the switching member (12) can provide variable electrical connections between the first lead (14) and second lead (16).

Abstract: A microelectromechanical system (MEMS) switch assembly (10) and a method of forming the MEMBS switch assembly (10) is provided that includes a switching member (12) having a first portion (34) that is at least partially formed with a first material having a first dielectric constant and a second portion (36) that is at least partially formed with a second material having a second dielectric constant. Furthermore, the switching member (12) further includes a first lead (14) spaced apart from a second lead (16) for contacting the switching member (12). In operation, the switching member (12) is configured for movement such that the first portion (34) and second portion (36) of the switching member (12) can provide variable electrical connections between the first lead (14) and second lead (16).

Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.

Abstract: A micro electro-mechanical systems device having variable capacitance is controllable over the full dynamic range and not subject to the “snap effect” common in the prior art. The device features an electrostatic driver (120) having a driver capacitor of fixed capacitance (121) in series with a second driver capacitor of variable capacitance (126). A MEMS variable capacitor (130) is controlled by applying an actuation voltage potential to the electrostatic driver (120). The electrostatic driver (120) and MEMS variable capacitor (130) are integrated in a single, monolithic device.

Abstract: A Micro-Electromechanical Systems (MEMS) device (100) having conductively filled vias (141). A MEMS component (124) is formed on a substrate (110). The substrate has conductively filled vias (140) extending therethrough. The MEMS component (124) is electrically coupled to the conductively filled vias (140). The MEMS component (124) is covered by a protective cap (150). An electrical interconnect (130) is formed on a bottom surface of the substrate (110) for transmission of electrical signals to the MEMS component (124), rather than using wirebonds.

Abstract: A micro electro-mechanical systems device having variable capacitance is controllable over the full dynamic range and not subject to the “snap effect” common in the prior art. The device features an electrostatic driver (120) having a driver capacitor of fixed capacitance (121) in series with a second driver capacitor of variable capacitance (126). A MEMS variable capacitor (130) is controlled by applying an actuation voltage potential to the electrostatic driver (120). The electrostatic driver (120) and MEMS variable capacitor (130) are integrated in a single, monolithic device.

Abstract: A micro electromechanical systems device having variable capacitance is controllable over the full dynamic range and not subject to the “snap effect” common in the prior art. The device features an electrostatic driver (120) having a driver capacitor of fixed capacitance (121) in series with a second driver capacitor of variable capacitance (126). A MEMS variable capacitor (130) is controlled by applying an actuation voltage potential to the electrostatic driver (120). The electrostatic driver (120) and MEMS variable capacitor (130) are integrated in a single, monolithic device.

Abstract: A manufacturable GaAs VFET process includes providing a doped GaAs substrate with a lightly doped first epitaxial layer thereon and a heavily doped second epitaxial layer positioned on the first epitaxial layer. A temperature tolerant conductive layer is positioned on the second epitaxial layer and patterned to define a plurality of elongated, spaced apart source areas. Using the patterned conductive layer, a plurality of gate trenches are etched into the first epitaxial layer adjacent the source areas. The bottoms of the gate trenches are implanted and activated to form gate areas. A gate contact is deposited in communication with the implanted gate areas, a source contact is deposited in communication with the patterned conductive layer overlying the source areas, and a drain contact is deposited on the rear surface of the substrate.

Abstract: A Micro-Electromechanical System (MEMS) switch (100) having a single, center hinge (120) which supports a membrane-type electrode (104) on a substrate (101). The single, center hinge (120) has a control electrode (104) coupled to the substrate (101) by an anchor (113), a hinge collar (121), a set of hinge arms (122, 123). The control electrode (104) has a shorting bar (106) coupled thereto and is electrically isolated from another control electrode (105), which is formed on the substrate (101). A travel stop (130) is positioned between the substrate and the control electrode (104). Another aspect of the present invention is a Single Pole, Double Throw (SPDT) switch (160) into which is incorporated the single, center hinge (170) and the travel stop (185, 186).

Abstract: An electrode structure for semiconductor devices includes first electrode material positioned in overlying relationship to the surface of a substrate so as to define a first side wall perpendicular thereto. A nonconductive side wall spacer is formed on the first side wall and defines a second side wall parallel to and spaced from the first side wall. Second electrode material is formed in overlying relationship to the substrate and on the second side wall so as to define a third side wall parallel to and spaced from the second side wall. The first and second electrode materials are connected as first and second electrodes in a common semiconductor device. Additional electrodes can be formed by forming electrode material on additional side walls.