Patents by Inventor Jeong Don Ihm

Jeong Don Ihm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10014039
    Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: July 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seon-Kyoo Lee, Jeong-Don Ihm, Byung-Hoon Jeong, Dae-Woon Kang
  • Patent number: 9904310
    Abstract: A regulator circuit includes a power transistor, a current mirror, a first NMOS transistor, a second NMOS transistor and a current source. The power transistor has a source connected to an external power supply voltage supply, a gate connected to a first node having a first voltage and a drain connected to a second node outputting an internal power supply voltage. A current mirror provides a first current to a third node having a second voltage and provides a first node with a second current. A first NMOS transistor has a drain connected to a first node, a gate receiving a first reference voltage and a source connected to a fourth node. A second NMOS transistor has a drain connected to a third node, a gate connected to a second node and a source connected to the fourth node.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECRONICS CO., LTD.
    Inventors: Jeong-Don Ihm, Siddharth Katare
  • Patent number: 9882565
    Abstract: A buffer circuit includes first and second current generators, a comparator, a differential driver, and an inverter. The first current generator outputs a first current corresponding to a reference voltage. The second current generator generates a limit current corresponding to an input limit voltage, and outputs a second current having a size equal to about half of the limit current. The sizes of the first current and the limit current are controlled by the feedback voltage. The comparator generates the feedback voltage by comparing the first and second currents. The differential driver generates an internal current, and controls the internal current based on the feedback voltage. The magnitudes of an upper limit value and a lower limit value of the internal current are substantially equal to each other with respect to a reference value. The inverter generates an output current by inverting the internal current based on supply voltage.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: January 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Siddharth Katare, Jeong-Don Ihm
  • Publication number: 20180004281
    Abstract: A reception interface circuit includes a reception buffer, a voltage generation circuit and a reception limiting circuit. The reception buffer receives an input signal through an input-output node to generate a buffer signal. The voltage generation circuit generates at least one control voltage based on a reflection characteristic at the input-output node. The reception limiting circuit is connected to the input-output node and limits at least one of a maximum voltage level and a minimum voltage level of the input signal based on the at least one control voltage. Power consumption may be reduced by limiting at least one of the maximum voltage level and the minimum voltage level of the input signal based on the reception characteristic at the input-output node using the reception limiting circuit, and an increased eye margin may be provided in comparison with a conventional termination circuit having the same power consumption.
    Type: Application
    Filed: February 7, 2017
    Publication date: January 4, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dae-Woon KANG, Siddharth KATARE, Jeong-Don IHM
  • Publication number: 20170316833
    Abstract: A single-ended sense amplifier and a memory device including the same are presented. A sense amplifier, which senses and amplifies data of a memory cell, may include a precharge circuit pre-charging a data line which is connected to the memory cell and provides a sensing voltage, and a reference line which provides a reference voltage, with a power supply voltage; a reference voltage generating circuit which generates the reference voltage by discharging the reference line based on a reference current, and adjusts an amount of the reference current based on the data of the memory cell; and a comparator which compares the sensing voltage and the reference voltage, and outputs a comparison result as the data of the memory cell.
    Type: Application
    Filed: March 8, 2017
    Publication date: November 2, 2017
    Inventors: Jeong-don IHM, Siddharth KATARE, Hyun-jin KIM
  • Publication number: 20170287535
    Abstract: A semiconductor device, includes at least a first memory chip, which includes at least a first buffer connected to receive an input signal and a reference voltage; at least a first reference voltage generator configured to output a reference voltage based on a first control code; and at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device. An output from the first buffer is input to the first self-training circuit, the first control code is output from the first self-training circuit into the first reference voltage generator, and the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.
    Type: Application
    Filed: October 25, 2016
    Publication date: October 5, 2017
    Inventors: Seon-Kyoo LEE, Jeong-Don IHM, Byung-Hoon JEONG, Dae-Woon KANG
  • Publication number: 20170288717
    Abstract: A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.
    Type: Application
    Filed: January 3, 2017
    Publication date: October 5, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seon-Kyoo LEE, Byung-Hoon JEONG, Jeong-Don IHM, Young-Don CHOI
  • Publication number: 20170288634
    Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.
    Type: Application
    Filed: January 18, 2017
    Publication date: October 5, 2017
    Inventors: DAE-WOON KANG, Jeong-Don IHM, Byung-Hoon JEONG, Young-Don CHOI
  • Patent number: 9653132
    Abstract: A semiconductor package includes an external electrode, an interface chip, and a semiconductor chip. The interface chip includes an external interface pad bonded to the external electrode, a plurality of internal interface pads, and an interface circuit coupled between the external interface pad and the plurality of internal interface pads. The semiconductor chip includes a signal pad that is selectively bonded to one of the plurality of internal interface pads. The interface circuit activates a connection between a selected pad, which corresponds to a pad that is bonded to the signal pad among the plurality of internal interface pads, and the external interface pad, and deactivates connections between unselected pads, which correspond to pads that are not bonded to the signal pad among the plurality of internal interface pads, and the external interface pad.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 16, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Hoon Na, Hyun-Jin Kim, Jeong-Don Ihm
  • Publication number: 20170060164
    Abstract: A regulator circuit includes a power transistor, a current minor, a first NMOS transistor, a second NMOS transistor and a current source. The power transistor has a source connected to external power supply voltage supply, a gate connected to a first node having a first voltage and a drain connected to a second node outputting an internal power supply voltage. A current minor provides a first current to a third node having a second voltage and provides a first node with a second current. A first NMOS transistor has a drain connected to a first node, a gate receiving a first reference voltage and a source connected to a fourth node. A second NMOS transistor has a drain connected to a third node, a gate connected to a second node and a source connected to the fourth node.
    Type: Application
    Filed: August 1, 2016
    Publication date: March 2, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Don Ihm, Siddharth Katare
  • Publication number: 20170052225
    Abstract: A semiconductor chip, a test system, and a method of testing the semiconductor chip. The semiconductor chip includes a pulse generator configured to generate a test pulse in response to a test request; a logic chain comprising a plurality of logic devices serially connected to each other and transferring the test pulse sequentially; and a detector configured to detect a logic level of an output signal of each of the logic devices and output a detection result indicating a degree of an inter-symbol interference (ISI).
    Type: Application
    Filed: June 1, 2016
    Publication date: February 23, 2017
    Inventors: Seon-kyoo LEE, Jeong-don IHM, Byung-hoon JEONG, Dae-woon KANG, Tae-sung LEE, Sang-lok KIM
  • Publication number: 20170048087
    Abstract: An equalizer circuit may include an equalizer controller and a plurality of equalizers. The equalizer controller may prove separate sets of enable signals, delay control signals and voltage control signals to the separate equalizers based on a control signal. The equalizers provide equalizer signals to separate connection nodes between separate pairs of logic circuits. An equalizer may be selectively activated based on a received enable signal. An equalizer may include a delay control circuit and a voltage control circuit. The delay control circuit may delay a received transfer signal to generate a delayed transfer signal based on a received delay control signal. The voltage control circuit may generate an equalizer signal based on the delayed transfer signal and a received voltage control signal. The equalizer circuit may reduce inter-symbol interference in the integrated circuit based on providing the equalizer signals to the connection nodes between the logic circuits.
    Type: Application
    Filed: April 15, 2016
    Publication date: February 16, 2017
    Inventors: SEON-KYOO LEE, Jeong-Don IHM, Anil KAVALA, Byung-Hoon JEONG
  • Publication number: 20170047925
    Abstract: A buffer circuit includes first and second current generators, a comparator, a differential driver, and an inverter. The first current generator outputs a first current corresponding to a reference voltage. The second current generator generates a limit current corresponding to an input limit voltage, and outputs a second current having a size equal to about half of the limit current. The sizes of the first current and the limit current are controlled by the feedback voltage. The comparator generates the feedback voltage by comparing the first and second currents. The differential driver generates an internal current, and controls the internal current based on the feedback voltage. The magnitudes of an upper limit value and a lower limit value of the internal current are substantially equal to each other with respect to a reference value. The inverter generates an output current by inverting the internal current based on supply voltage.
    Type: Application
    Filed: April 28, 2016
    Publication date: February 16, 2017
    Inventors: SIDDHARTH KATARE, JEONG-DON IHM
  • Publication number: 20160358655
    Abstract: A semiconductor package includes an external electrode, an interface chip, and a semiconductor chip. The interface chip includes an external interface pad bonded to the external electrode, a plurality of internal interface pads, and an interface circuit coupled between the external interface pad and the plurality of internal interface pads. The semiconductor chip includes a signal pad that is selectively bonded to one of the plurality of internal interface pads. The interface circuit activates a connection between a selected pad, which corresponds to a pad that is bonded to the signal pad among the plurality of internal interface pads, and the external interface pad, and deactivates connections between unselected pads, which correspond to pads that are not bonded to the signal pad among the plurality of internal interface pads, and the external interface pad.
    Type: Application
    Filed: February 24, 2016
    Publication date: December 8, 2016
    Inventors: DAE-HOON NA, HYUN-JIN KIM, JEONG-DON IHM
  • Patent number: 9461656
    Abstract: An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: October 4, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hye-Yoon Joo, Seung-Jun Bae, Young-Soo Sohn, Ho-Sung Song, Jeong-Don Ihm
  • Publication number: 20150213873
    Abstract: An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.
    Type: Application
    Filed: December 2, 2014
    Publication date: July 30, 2015
    Inventors: Hye-Yoon JOO, Seung-Jun BAE, Young-Soo SOHN, Ho-Sung SONG, Jeong-Don IHM
  • Patent number: 6232811
    Abstract: There is provided a circuit for controlling the setup/hold time of a semiconductor device, including: a setup/hold on signal generator for generating a setup/hold on signal of the semiconductor device; a comparison signal generator for converting the difference between pulse widths of the setup on signal and hold on signal of the setup/hold on signal generator into the voltage difference across an inner capacitor, to generate a comparison signal for the setup/hold time; a comparison signal detector for detecting the comparison signal generated by the comparison signal generator and amplifying it to a predetermined level; a clock delay path selection signal generator for generating a clock delay path selection signal according to the level of the signal detected by the comparison signal detector; and a clock/command signal processor for outputting a clock signal and command signal applied to input pads as an inner clock signal and inner command signal whose delays are compensated according to the clock delay p
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: May 15, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Jeong Don Ihm