Abstract: A method of fabricating a semiconductor device comprises forming first and second align keys in a wafer, the second align key apart from the first align key, forming third and fourth align keys in the wafer, the third align key apart from the second align key, the fourth align key apart from the third align key, forming a fifth align key in the wafer, the fifth align key apart from the fourth align key, forming a first line pattern in the wafer using the second and third align keys, forming a second line pattern in the wafer using the fourth and fifth align keys, forming a first interposer including the first line pattern by cutting a space between the first and second align keys, and forming a second interposer, the second interposer including the second line pattern by cutting a space between the third and fourth align keys.

Abstract: A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.

Abstract: A semiconductor device including a first electrode on a substrate, a second electrode on the first electrode, a first dielectric layer between the first electrode and the second electrode; a third electrode on the second electrode, a second dielectric layer between the second electrode and the third electrode, and a first contact plug penetrating the third electrode and contacting the first electrode, the first contact plug contacts a top surface of the third electrode and a side surface of the third electrode.

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a first dielectric layer including a first pad, a second dielectric layer on the first dielectric layer, a through electrode that penetrates the second dielectric layer and is electrically connected to the first pad, an upper passivation layer on the second dielectric layer, a second pad on the upper passivation layer, and an upper barrier layer between the upper passivation layer and the second pad. The first pad and the through electrode include a first material. The second pad includes a second material that is different from the first material of the first pad and the through electrode. The second pad includes a first part on the upper passivation layer, and a second part that extends from the first part into the upper passivation layer and is connected to the through electrode.

Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, a through contact below the first metal layer penetrating the connection region, an upper portion of the through contact protruding above the etch stop layer, and a protection insulating pattern on the etch stop layer covering the upper portion of the through contact. The protection insulating pattern covers an upper side surface of the through contact and a top surface of the through contact.

Abstract: A semiconductor device includes a substrate having a first region, a second region, a first buffer region, and a second buffer region. A plurality of conductive lines is disposed on the first region of the substrate. An inductor is disposed on the second region of the substrate, and a dummy pattern is disposed on the first buffer region of the substrate. The first buffer region is provided between the first region and the second region. The second buffer region is provided between the first buffer region and the second region.

Abstract: A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.

Abstract: A method of fabricating a semiconductor device comprises forming first and second align keys in a wafer, the second align key apart from the first align key, forming third and fourth align keys in the wafer, the third align key apart from the second align key, the fourth align key apart from the third align key, forming a fifth align key in the wafer, the fifth align key apart from the fourth align key, forming a first line pattern in the wafer using the second and third align keys, forming a second line pattern in the wafer using the fourth and fifth align keys, forming a first interposer including the first line pattern by cutting a space between the first and second align keys, and forming a second interposer, the second interposer including the second line pattern by cutting a space between the third and fourth align keys.

Abstract: Provided is an interposer structure. The interposer structure comprises an interposer substrate, an interlayer insulating film which covers a top surface of the interposer substrate, a capacitor structure in the interlayer insulating film and a wiring structure including a first wiring pattern and a second wiring pattern spaced apart from the first wiring pattern, on the interlayer insulating film, wherein the capacitor structure includes an upper electrode connected to the first wiring pattern, a lower electrode connected to the second wiring pattern, and a capacitor dielectric film between the upper electrode and the lower electrode.

Abstract: The method of manufacturing an interposer includes providing a substrate including a first region and a second region adjacent to the first region, forming a first mold structure on the substrate, forming a photoresist layer on the first mold structure, forming a first transfer pattern over the photoresist layer on the first region, using a first photomask, forming a second transfer pattern over the photoresist layer on the second region, using the first photomask, forming a mask pattern on the first mold structure, using the first transfer pattern and the second transfer pattern and forming a first trench and a second trench in the first mold structure, using the mask pattern, the first trench being formed in the first region, and the second trench being formed in the second region.

Abstract: Semiconductor devices including a capacitor in which electrostatic capacity is improved by a simplified process and/or methods for fabricating the same are provided. The semiconductor device including an insulating structure defining a first trench on a substrate, a first conductive layer in the insulating structure, a first portion of an upper surface of the first conductive layer exposed by the first trench, a capacitor structure including a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, the first electrode pattern extending along sidewalls and a bottom surface of the first trench and an upper surface of the insulating structure, and a first wiring pattern on the capacitor structure may be provided.

Abstract: A semiconductor device including a substrate having a first surface and a second surface facing the first surface, the substrate having a via hole, the via hole extending from the first surface of the substrate toward the second surface of the substrate, a through via in the via hole, a semiconductor component on the first surface of the substrate, and an internal buffer structure spaced apart from the via hole and between the via hole and the semiconductor component, the internal buffer structure extending from the first surface of the substrate toward an inside of the substrate, a top end of the internal buffer structure being at a level higher than a top end of the through via may be provided.

Abstract: A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.

Abstract: A semiconductor device includes a first lower pad and a second lower pad on a substrate, a first electrode being in contact with a top surface of the first lower pad, a second electrode disposed on the first electrode and being in contact with a top surface of the second lower pad, a dielectric layer between the first electrode and the second electrode, and a third electrode on the second electrode.

Abstract: A semiconductor device includes a substrate having a first region, a second region, a first buffer region, and a second buffer region. A plurality of conductive lines is disposed on the first region of the substrate. An inductor is disposed on the second region of the substrate, and a dummy pattern is disposed on the first buffer region of the substrate. The first buffer region is provided between the first region and the second region. The second buffer region is provided between the first buffer region and the second region.

Abstract: A semiconductor device including a first electrode on a substrate, a second electrode on the first electrode, a first dielectric layer between the first electrode and the second electrode; a third electrode on the second electrode, a second dielectric layer between the second electrode and the third electrode, and a first contact plug penetrating the third electrode and contacting the first electrode, the first contact plug contacts a top surface of the third electrode and a side surface of the third electrode.

Abstract: Semiconductor devices including a capacitor in which electrostatic capacity is improved by a simplified process and/or methods for fabricating the same are provided. The semiconductor device including an insulating structure defining a first trench on a substrate, a first conductive layer in the insulating structure, a first portion of an upper surface of the first conductive layer exposed by the first trench, a capacitor structure including a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, the first electrode pattern extending along sidewalls and a bottom surface of the first trench and an upper surface of the insulating structure, and a first wiring pattern on the capacitor structure may be provided.

Abstract: A semiconductor device including a substrate having a first surface and a second surface facing the first surface, the substrate having a via hole, the via hole extending from the first surface of the substrate toward the second surface of the substrate, a through via in the via hole, a semiconductor component on the first surface of the substrate, and an internal buffer structure spaced apart from the via hole and between the via hole and the semiconductor component, the internal buffer structure extending from the first surface of the substrate toward an inside of the substrate, a top end of the internal buffer structure being at a level higher than a top end of the through via may be provided.

Abstract: A semiconductor device, comprising: a substrate which includes an active circuit region, and a boundary region surrounding the active circuit region, the boundary region including an edge portion of the substrate; a first lower conductive pattern disposed on the substrate of the boundary region; and a first upper conductive pattern connected to the first lower conductive pattern over the first lower conductive pattern, wherein the first upper conductive pattern includes a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness, and the third portion of the first upper conductive pattern is connected to the first lower conductive pattern, is provided.

Abstract: A semiconductor device includes a first electrode which includes a first main portion, and a first extension that extends from the first main portion, and a dielectric layer which surrounds a sidewall and a bottom surface of the first main portion, wherein the first main portion includes a first portion having a first depth, and a second portion having a second depth deeper than the first depth.