Abstract: Provided is an interposer structure. The interposer structure comprises an interposer substrate, an interlayer insulating film which covers a top surface of the interposer substrate, a capacitor structure in the interlayer insulating film and a wiring structure including a first wiring pattern and a second wiring pattern spaced apart from the first wiring pattern, on the interlayer insulating film, wherein the capacitor structure includes an upper electrode connected to the first wiring pattern, a lower electrode connected to the second wiring pattern, and a capacitor dielectric film between the upper electrode and the lower electrode.

Abstract: The method of manufacturing an interposer includes providing a substrate including a first region and a second region adjacent to the first region, forming a first mold structure on the substrate, forming a photoresist layer on the first mold structure, forming a first transfer pattern over the photoresist layer on the first region, using a first photomask, forming a second transfer pattern over the photoresist layer on the second region, using the first photomask, forming a mask pattern on the first mold structure, using the first transfer pattern and the second transfer pattern and forming a first trench and a second trench in the first mold structure, using the mask pattern, the first trench being formed in the first region, and the second trench being formed in the second region.

Abstract: Semiconductor devices including a capacitor in which electrostatic capacity is improved by a simplified process and/or methods for fabricating the same are provided. The semiconductor device including an insulating structure defining a first trench on a substrate, a first conductive layer in the insulating structure, a first portion of an upper surface of the first conductive layer exposed by the first trench, a capacitor structure including a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, the first electrode pattern extending along sidewalls and a bottom surface of the first trench and an upper surface of the insulating structure, and a first wiring pattern on the capacitor structure may be provided.

Abstract: A semiconductor device including a substrate having a first surface and a second surface facing the first surface, the substrate having a via hole, the via hole extending from the first surface of the substrate toward the second surface of the substrate, a through via in the via hole, a semiconductor component on the first surface of the substrate, and an internal buffer structure spaced apart from the via hole and between the via hole and the semiconductor component, the internal buffer structure extending from the first surface of the substrate toward an inside of the substrate, a top end of the internal buffer structure being at a level higher than a top end of the through via may be provided.

Abstract: A semiconductor device includes a substrate, a first electrode including a first hole, a first dielectric layer on an upper surface of the first electrode and on an inner surface of the first hole, a second electrode on the first dielectric layer, a second dielectric layer on the second electrode, a third electrode on the second dielectric layer and including a second hole, and a first contact plug extending through the second electrode and the second dielectric layer and extending through the first hole and the second hole. A sidewall of the first contact plug is isolated from direct contact with the sidewall of the first hole and a sidewall of the second hole, and has a step portion located adjacent to an upper surface of the second electrode.

Abstract: A semiconductor device includes a first lower pad and a second lower pad on a substrate, a first electrode being in contact with a top surface of the first lower pad, a second electrode disposed on the first electrode and being in contact with a top surface of the second lower pad, a dielectric layer between the first electrode and the second electrode, and a third electrode on the second electrode.

Abstract: A semiconductor device includes a substrate having a first region, a second region, a first buffer region, and a second buffer region. A plurality of conductive lines is disposed on the first region of the substrate. An inductor is disposed on the second region of the substrate, and a dummy pattern is disposed on the first buffer region of the substrate. The first buffer region is provided between the first region and the second region. The second buffer region is provided between the first buffer region and the second region.

Abstract: A semiconductor device including a first electrode on a substrate, a second electrode on the first electrode, a first dielectric layer between the first electrode and the second electrode; a third electrode on the second electrode, a second dielectric layer between the second electrode and the third electrode, and a first contact plug penetrating the third electrode and contacting the first electrode, the first contact plug contacts a top surface of the third electrode and a side surface of the third electrode.

Abstract: Semiconductor devices including a capacitor in which electrostatic capacity is improved by a simplified process and/or methods for fabricating the same are provided. The semiconductor device including an insulating structure defining a first trench on a substrate, a first conductive layer in the insulating structure, a first portion of an upper surface of the first conductive layer exposed by the first trench, a capacitor structure including a first electrode pattern on the first conductive layer, a dielectric pattern on the first electrode pattern, and a second electrode pattern on the dielectric pattern, the first electrode pattern extending along sidewalls and a bottom surface of the first trench and an upper surface of the insulating structure, and a first wiring pattern on the capacitor structure may be provided.

Abstract: A semiconductor device including a substrate having a first surface and a second surface facing the first surface, the substrate having a via hole, the via hole extending from the first surface of the substrate toward the second surface of the substrate, a through via in the via hole, a semiconductor component on the first surface of the substrate, and an internal buffer structure spaced apart from the via hole and between the via hole and the semiconductor component, the internal buffer structure extending from the first surface of the substrate toward an inside of the substrate, a top end of the internal buffer structure being at a level higher than a top end of the through via may be provided.

Abstract: A semiconductor device, comprising: a substrate which includes an active circuit region, and a boundary region surrounding the active circuit region, the boundary region including an edge portion of the substrate; a first lower conductive pattern disposed on the substrate of the boundary region; and a first upper conductive pattern connected to the first lower conductive pattern over the first lower conductive pattern, wherein the first upper conductive pattern includes a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness, and the third portion of the first upper conductive pattern is connected to the first lower conductive pattern, is provided.

Abstract: A semiconductor device includes a first electrode which includes a first main portion, and a first extension that extends from the first main portion, and a dielectric layer which surrounds a sidewall and a bottom surface of the first main portion, wherein the first main portion includes a first portion having a first depth, and a second portion having a second depth deeper than the first depth.

Abstract: A semiconductor device includes a first electrode which includes a first main portion, and a first extension that extends from the first main portion, and a dielectric layer which surrounds a sidewall and a bottom surface of the first main portion, wherein the first main portion includes a first portion having a first depth, and a second portion having a second depth deeper than the first depth.

Abstract: A semiconductor device, comprising: a substrate which includes an active circuit region, and a boundary region surrounding the active circuit region, the boundary region including an edge portion of the substrate; a first lower conductive pattern disposed on the substrate of the boundary region; and a first upper conductive pattern connected to the first lower conductive pattern over the first lower conductive pattern, wherein the first upper conductive pattern includes a first portion having a first thickness, a second portion having a second thickness greater than the first thickness, and a third portion having a third thickness greater than the second thickness, and the third portion of the first upper conductive pattern is connected to the first lower conductive pattern, is provided.

Abstract: A wiring structure includes a substrate, a lower insulation layer on the substrate, a lower wiring in the lower insulation layer, a first etch-stop layer covering the lower wiring and including a metallic dielectric material, a second etch-stop layer on the first etch-stop layer and the lower insulation layer, an insulating interlayer on the second etch-stop layer, and a conductive pattern extending through the insulating interlayer, the second etch-stop layer and the first etch-stop layer and electrically connected to the lower wiring.

Abstract: Semiconductor devices may include an internal circuit, a sealing region surrounding the internal circuit, and a decoupling capacitor region in the sealing region. The decoupling capacitor region may include decoupling capacitors. Each of the decoupling capacitors may include a first capacitor metal wiring pattern connected to a high power supply line, a second capacitor metal wiring pattern spaced apart from the first capacitor metal wiring pattern and connected to a low power supply line, and a dielectric pattern between the first capacitor metal wiring pattern and the second capacitor metal wiring pattern.

Abstract: A test structure for manufacturing a semiconductor device includes a test element, a first pad connected to the test element, and a second pad connected to the test element. A first wire is connected to the test element, and the first wire and the test element are part of a first layer disposed on a semiconductor substrate. A second wire is connected to the first wire, and is part of a second layer disposed on the semiconductor substrate, and the second layer is different from the first layer.

Abstract: There are disclosed an apparatus for assembling a 3D model including a key input unit configured to generate a variety of key inputs for 3D model assembling or key data based on touch input on a screen; a control unit configured to drive an application to implement 3D model assembling based on the key input from the key input unit; a 3D model unit configured to provide a menu screen for 3D model assembling, when driven by the control unit, to display a screen of parts for a 3D model selected as an assembling object based on the touch or key input on the menu screen and to assemble parts selected from the part screen in successive steps to finish the 3D model; and a display unit configured to display successive screens based on the 3D model assembling performed by the 3D model unit.

Abstract: In a method of forming a wiring structure, a first mask having a first opening including a first portion extending in a second direction and a second portion extending in a first direction is formed. A second mask including a second opening overlapping the first portion of the first opening and third openings each overlapping the second portion of the first opening is designed. The second mask is fabricated to include a fourth opening by enlarging the second opening. The fourth opening overlaps a boundary between the first and second portions of the first opening. An insulating interlayer is etched using the first and second masks to form first and second via holes corresponding to the fourth and third openings, and a trench corresponding to the first opening. First and second vias and a wiring are formed to fill the first and second via holes and the trench.

Abstract: A test structure for manufacturing a semiconductor device includes a test element, a first pad connected to the test element, and a second pad connected to the test element. A first wire is connected to the test element, and the first wire and the test element are part of a first layer disposed on a semiconductor substrate. A second wire is connected to the first wire, and is part of a second layer disposed on the semiconductor substrate, and the second layer is different from the first layer.