Patents by Inventor Jeong-Nam Han

Jeong-Nam Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10424503
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: September 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Patent number: 10297474
    Abstract: A chemical supplier includes a chemical reservoir containing a chemical mixture at a room temperature, an inner space of the chemical reservoir being separated from surroundings, a supply line through which the chemical mixture is supplied to a process chamber from the chemical reservoir, an inline heater positioned on the supply line and heating the chemical mixture in the supply line to a process temperature, and a power source driving the chemical mixture to move the chemical mixture toward the process chamber.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Kee-Sang Kwon, Doo-Sung Yun, Won-Sang Choi
  • Publication number: 20190091828
    Abstract: A method of controlling a chemical mechanical polishing (CMP) process, a temperature control, and a CMP apparatus, the method including measuring actual temperatures of at least two regions in a platen in real time during the CMP process in which a polishing pad attached to the platen polishes a substrate held by a polishing head using slurry and deionized water; receiving the measured actual temperatures of the regions; and individually controlling the actual temperatures of the regions in real time during the CMP process to provide the regions with a predetermined set CMP process temperature.
    Type: Application
    Filed: March 20, 2018
    Publication date: March 28, 2019
    Inventors: Suk-Hoon JEONG, Sang-Hak LEE, Geun-Kyu CHOI, Chang-Sun HWANG, Tae-Young KWON, Young-Sang KIM, Hyung-Kyu JIN, Jeong-Nam HAN
  • Patent number: 10192973
    Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: January 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Ha-Young Jeon, Byung-Kwon Cho, Jeong-Nam Han
  • Patent number: 10090190
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 2, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sang Youn, Myung-Geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Publication number: 20180174889
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Application
    Filed: January 31, 2018
    Publication date: June 21, 2018
    Inventors: Young-Sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Patent number: 9812367
    Abstract: A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced from each other on a substrate, forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench, forming first and second lower conductive layers on the first and second dielectric layers, respectively, forming first and second capping layers on the first and second lower conductive layer, respectively, performing a heat treatment after the first and second capping layers have been formed, removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment, and forming first and second metal gate structures on the first and second dielectric layers, respectively.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Kim, Ji-Hwan An, Kwang-Yul Lee, Tae-Won Ha, Jeong-Nam Han
  • Publication number: 20170301581
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Application
    Filed: June 29, 2017
    Publication date: October 19, 2017
    Inventors: Young-Sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Patent number: 9786764
    Abstract: A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: October 10, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-Jin Park, Chung-Hwan Shin, Sung-Woo Kang, Young-Mook Oh, Sun-Jung Lee, Jeong-Nam Han
  • Patent number: 9754806
    Abstract: Provided are an apparatus and method for treating wafers using a supercritical fluid. The wafer treatment apparatus includes a plurality of chambers; a first supply supplying a first fluid in a supercritical state; a second supply supplying a mixture of the first fluid and a second fluid; a plurality of first and second valves; and a controller selecting a first chamber of the plurality of chambers for wafer treatment to control the open/closed state of each of the plurality of first valves so that the first fluid can be supplied only to the first chamber of the plurality of chambers and selecting a second chamber of the plurality of chambers to control the open/closed state of each of the plurality of second valves so that the mixture of the first fluid and a second fluid can be supplied only to the second chamber of the plurality of chambers.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: September 5, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo-San Lee, Chang-ki Hong, Kun-tack Lee, Jeong-nam Han
  • Patent number: 9728535
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Publication number: 20160359017
    Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.
    Type: Application
    Filed: August 17, 2016
    Publication date: December 8, 2016
    Inventors: Sang-Jine PARK, Bo-Un YOON, Ha-Young JEON, Byung-Kwon CHO, Jeong-Nam HAN
  • Patent number: 9466697
    Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: October 11, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Myung-Geun Song
  • Patent number: 9443979
    Abstract: A semiconductor device includes a gate spacer defining a trench. The trench includes a first part and a second part sequentially positioned on a substrate. An inner surface of the first part has a slope of an acute angle and an inner surface of the second part has a slope of a right angle or obtuse angle with respect to the substrate. A gate electrode fills at least a portion of the trench.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: September 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Ha-Young Jeon, Byung-Kwon Cho, Jeong-Nam Han
  • Publication number: 20160181243
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Application
    Filed: March 2, 2016
    Publication date: June 23, 2016
    Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Publication number: 20160141417
    Abstract: A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction.
    Type: Application
    Filed: October 22, 2015
    Publication date: May 19, 2016
    Inventors: Chan-Jin PARK, Chung-Hwan SHIN, Sung-Woo KANG, Young-Mook OH, Sun-Jung LEE, Jeong-Nam HAN
  • Patent number: 9305825
    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-sang Youn, Myung-geun Song, Ji-hoon Cha, Jae-jik Baek, Bo-un Yoon, Jeong-nam Han
  • Publication number: 20150364574
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure including a dummy gate insulation layer pattern, a dummy gate electrode and a gate mask sequentially stacked are formed on a substrate. An interlayer insulating layer including tonen silazane (TOSZ) is formed on the substrate to cover the dummy gate structure. An upper portion of the interlayer insulating layer is planarized until a top surface of the gate mask is exposed to form an interlayer insulating layer pattern. The exposed gate mask, and the dummy gate electrode and the dummy gate insulation layer pattern under the gate mask are removed to form an opening exposing a top surface of the substrate. The dummy gate insulation layer pattern is removed using an etchant including hydrogen fluoride (HF), but the interlayer insulating layer pattern remains. A gate structure is formed to fill the opening.
    Type: Application
    Filed: December 22, 2014
    Publication date: December 17, 2015
    Inventors: Ju-Youn KIM, Dong-Hyun ROH, Sang-Duk PARK, Il-Young YOON, Jeong-Nam HAN, Jong-Mil YOUN
  • Publication number: 20150357426
    Abstract: A method of fabricating a semiconductor device includes forming an inter-metal dielectric layer including a first trench and a second trench which are spaced from each other on a substrate, forming a first dielectric layer along the sides and bottom of the first trench, forming a second dielectric layer along the sides and bottom of the second trench, forming first and second lower conductive layers on the first and second dielectric layers, respectively, forming first and second capping layers on the first and second lower conductive layer, respectively, performing a heat treatment after the first and second capping layers have been formed, removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment, and forming first and second metal gate structures on the first and second dielectric layers, respectively.
    Type: Application
    Filed: February 13, 2015
    Publication date: December 10, 2015
    Inventors: JU-YOUN KIM, JI-HWAN AN, KWANG-YUL LEE, TAE-WON HA, JEONG-NAM HAN
  • Publication number: 20150279991
    Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.
    Type: Application
    Filed: May 26, 2015
    Publication date: October 1, 2015
    Inventors: Sang-Jine PARK, Bo-Un YOON, Jeong-Nam HAN, Myung-Geun SONG