Patents by Inventor Jeong Tae Hwang
Jeong Tae Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960755Abstract: A semiconductor memory device comprises: first storage logic configured to store, as first addresses, ‘K’ addresses having different values among input addresses applied during the enable period of a reference signal, second storage logic configured to store, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended among the input addresses, an order controller configured to determine a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together, and refresh operation logic configured to apply the mixed addresses according to the second output order, to a target refresh operation.Type: GrantFiled: December 13, 2021Date of Patent: April 16, 2024Assignee: SK hynix Inc.Inventors: Woongrae Kim, Kwi Dong Kim, Chul Moon Jung, Jeong Tae Hwang
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Publication number: 20240097235Abstract: A composite pad and a battery cell assembly and a battery module including the composite pad are disclosed. In some implementations, the battery cell assembly comprises a plurality of battery cells arranged in a direction, and one or more pads, each pad disposed between two adjacent battery cells of the plurality of battery cells, at least one of the one or more pads including a pad body with elasticity, and a heat generating part coupled to the pad body and connected to an edge of the at least one of the one or more pads and configured to generate heat upon application of electric power to the heat generating part.Type: ApplicationFiled: July 7, 2023Publication date: March 21, 2024Inventors: Jeong Tae HWANG, You Kyung PARK, Sang Gi SHIM, So Mi LEE
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Publication number: 20240086531Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Joon-Woo CHOI, Jeong-Tae HWANG
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Patent number: 11861000Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.Type: GrantFiled: April 7, 2020Date of Patent: January 2, 2024Assignee: SK hynix Inc.Inventors: Joon-Woo Choi, Jeong-Tae Hwang
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Patent number: 11768414Abstract: A display device includes first and second gate lines extending in a first direction; first and second data lines extending in a second direction and crossing the first and second gate lines; and a first horizontal pixel row including first, second, and third sub-pixels sequentially arranged in the first direction, wherein the first sub-pixel is connected to the first gate line and the first data line, the second sub-pixel is connected to the second gate line and the first data line, and the third sub-pixel is connected to the first gate line and the second data line.Type: GrantFiled: December 22, 2021Date of Patent: September 26, 2023Assignee: LG DISPLAY CO., LTD.Inventors: Jeong-Tae Hwang, Seung-Tae Kim
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Publication number: 20230198047Abstract: A composite pad and a battery module including the same are disclosed. The composite pad is a pad including a first pad surface and a second pad surface positioned opposite the first pad surface. The composite pad includes a pad body with elasticity, and a heat conduction part with thermal conductivity coupled to the pad body and connected to an edge of the pad. The pad body forms at least a portion of the first pad surface and forms at least a portion of the second pad surface.Type: ApplicationFiled: December 20, 2022Publication date: June 22, 2023Inventors: Jeong Tae HWANG, Jung Hyun SEO, Eun Sam CHO, Ju Young CHOI
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Patent number: 11651812Abstract: A memory system includes: a memory controller suitable for: generating a normal refresh command and a target refresh command when a number of inputs of an active command reaches a certain number, and providing the active command, the normal refresh command, the target refresh command, and an address; and a memory device including a plurality of banks and suitable for: performing a target refresh operation on one or more word lines of at least one bank in response to the target refresh command, determining a row hammer risk level per bank by counting, within a periodic interval, a number of inputs of the target refresh command per bank based on the address, and performing a hidden refresh operation corresponding to the row hammer risk level per bank in response to the normal refresh command.Type: GrantFiled: July 1, 2021Date of Patent: May 16, 2023Assignee: SK hynix Inc.Inventors: Woongrae Kim, Duck Hwa Hong, Jeong Tae Hwang
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Publication number: 20220270672Abstract: A memory system includes: a memory controller suitable for: generating a normal refresh command and a target refresh command when a number of inputs of an active command reaches a certain number, and providing the active command, the normal refresh command, the target refresh command, and an address; and a memory device including a plurality of banks and suitable for: performing a target refresh operation on one or more word lines of at least one bank in response to the target refresh command, determining a row hammer risk level per bank by counting, within a periodic interval, a number of inputs of the target refresh command per bank based on the address, and performing a hidden refresh operation corresponding to the row hammer risk level per bank in response to the normal refresh command.Type: ApplicationFiled: July 1, 2021Publication date: August 25, 2022Inventors: Woongrae KIM, Duck Hwa HONG, Jeong Tae HWANG
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Patent number: 11409668Abstract: A memory module includes: a plurality of memories, wherein each of the memories comprises: an encryption key storage circuit suitable for storing an encryption key; an address encryption circuit suitable for generating an encrypted address by encrypting an address transferred from a memory controller by using the encryption key stored in the encryption key storage circuit; and a cell array accessed by the encrypted address, wherein the encryption key storage circuits of the memories store different encryption keys.Type: GrantFiled: December 27, 2019Date of Patent: August 9, 2022Assignee: SK hynix Inc.Inventors: Woongrae Kim, Sang-Kwon Lee, Jung-Hyun Kim, Jong-Hyun Park, Jong-Ho Son, Mi-Hyun Hwang, Jeong-Tae Hwang
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Publication number: 20220206351Abstract: A display device includes first and second gate lines extending in a first direction; first and second data lines extending in a second direction and crossing the first and second gate lines; and a first horizontal pixel row including first, second, and third sub-pixels sequentially arranged in the first direction, wherein the first sub-pixel is connected to the first gate line and the first data line, the second sub-pixel is connected to the second gate line and the first data line, and the third sub-pixel is connected to the first gate line and the second data line.Type: ApplicationFiled: December 22, 2021Publication date: June 30, 2022Applicant: LG Display Co., Ltd.Inventors: Jeong-Tae HWANG, Seung-Tae KIM
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Publication number: 20220188015Abstract: A semiconductor memory device comprises: first storage logic configured to store, as first addresses, ‘K’ addresses having different values among input addresses applied during the enable period of a reference signal, second storage logic configured to store, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended among the input addresses, an order controller configured to determine a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together, and refresh operation logic configured to apply the mixed addresses according to the second output order, to a target refresh operation.Type: ApplicationFiled: December 13, 2021Publication date: June 16, 2022Inventors: Woongrae KIM, Kwi Dong KIM, Chul Moon JUNG, Jeong Tae HWANG
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Publication number: 20210042407Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.Type: ApplicationFiled: April 7, 2020Publication date: February 11, 2021Inventors: Joon-Woo CHOI, Jeong-Tae HWANG
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Publication number: 20200356495Abstract: A memory module includes: a plurality of memories, wherein each of the memories comprises: an encryption key storage circuit suitable for storing an encryption key; an address encryption circuit suitable for generating an encrypted address by encrypting an address transferred from a memory controller by using the encryption key stored in the encryption key storage circuit; and a cell array accessed by the encrypted address, wherein the encryption key storage circuits of the memories store different encryption keys.Type: ApplicationFiled: December 27, 2019Publication date: November 12, 2020Inventors: Woongrae KIM, Sang-Kwon LEE, Jung-Hyun KIM, Jong-Hyun PARK, Jong-Ho SON, Mi-Hyun HWANG, Jeong-Tae HWANG
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Publication number: 20200343535Abstract: A ceria-carbon-sulfur (CeO2—C—S) composite including a ceria-carbon (CeO2—C) composite in which cylindrical carbon materials having ceria (CeO2) particles bonded to surfaces thereof are entangled and interconnected to each other in three dimensions; and sulfur introduced into at least a portion of an outer surface and an inside of the ceria-carbon composite, a method for preparing the same, and positive electrode for a lithium-sulfur battery and a lithium-sulfur battery including the same.Type: ApplicationFiled: March 13, 2019Publication date: October 29, 2020Applicants: LG CHEM, LTD., SOGANG UNIVERSITY RESEARCH FOUNDATIONInventors: Seungbo YANG, Kwonnam SOHN, Jun Hyuk MOON, Doo Kyung YANG, Donghee GUEON, Jeong Tae HWANG
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Patent number: 10614873Abstract: A memory device may include first and second latch sections configured to respectively store a target address and a recent input address, a comparison unit configured to compare an input address with the target address and the recent input address respectively stored in the first and second latch sections, and output a resultant signal, a counting section configured to increase a count corresponding to the recent address stored in the second latch section in response to the resultant signal, and a control unit configured to check the count of the counting section and update the input address to the second latch section in response to the resultant signal.Type: GrantFiled: October 9, 2017Date of Patent: April 7, 2020Assignee: SK hynix Inc.Inventors: Woo-Young Lee, Duck-Hwa Hong, Jung-Hyun Kim, Jae-Hoon Cha, Jeong-Tae Hwang
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Patent number: 10109362Abstract: A semiconductor device includes a fuse array section suitable for performing program and read operations; a control signal generation section suitable for generating a precharge control signal and a word line control signal; a bit line control section suitable for controlling a precharge operation of a bit line in response to the precharge control signal and a source signal; and a word line control section suitable for controlling activation of a program word line and a read word line for performing the program and read operations in response to the word line control signal, wherein the control signal generation section controls the word line control signal to be activated after a predetermined time from the activation of the precharge control signal.Type: GrantFiled: June 2, 2017Date of Patent: October 23, 2018Assignee: SK Hynix Inc.Inventor: Jeong-Tae Hwang
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Patent number: 10037793Abstract: A semiconductor memory device includes: a high frequency signal control unit for receiving an external command address signal, removing noise and glitch from the external command address signal and outputting a first command address signal; a pulse width control unit for controlling a pulse width of the first command address signal or maintaining the pulse width of the first command address signal and outputting a second command address signal with a predetermined pulse width; a refresh operation control unit for generating a row address for a refresh operation in response to the second command address signal; and a memory cell array for performing the a refresh operation in response to the row address.Type: GrantFiled: January 5, 2017Date of Patent: July 31, 2018Assignee: SK Hynix Inc.Inventors: Sang-Ah Hyun, Jeong-Tae Hwang
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Publication number: 20180182445Abstract: A memory device may include first and second latch sections configured to respectively store a target address and a recent input address, a comparison unit configured to compare an input address with the target address and the recent input address respectively stored in the first and second latch sections, and output a resultant signal, a counting section configured to increase a count corresponding to the recent address stored in the second latch section in response to the resultant signal, and a control unit configured to check the count of the counting section and update the input address to the second latch section in response to the resultant signal.Type: ApplicationFiled: October 9, 2017Publication date: June 28, 2018Inventors: Woo-Young LEE, Duck-Hwa HONG, Jung-Hyun KIM, Jae-Hoon CHA, Jeong-Tae HWANG
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Patent number: 9960770Abstract: A semiconductor integrated circuit device may include a target PMOS transistor, a target NMOS transistor, a first stress-applying circuit, a second stress-applying circuit, a third stress-applying circuit and a fourth stress-applying circuit. An inverter may include the target PMOS transistor and the NMOS transistor. The first stress-applying circuit may be configured to apply a first DC level to a gate of the target PMOS transistor. The second stress-applying circuit may be configured to apply a second DC level to a gate of the target NMOS transistor. The third stress-applying circuit may be configured to apply an AC voltage shape to the gate of the target NMOS transistor. The fourth stress-applying circuit may be configured to apply the AC voltage to a drain of the target NMOS transistor.Type: GrantFiled: February 10, 2016Date of Patent: May 1, 2018Assignee: SK hynix Inc.Inventors: Jeong Tae Hwang, Jin Youp Cha, Young Sik Heo
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Publication number: 20180108424Abstract: A semiconductor device includes a fuse array section suitable for performing program and read operations; a control signal generation section suitable for generating a precharge control signal and a word line control signal; a bit line control section suitable for controlling a precharge operation of a bit line in response to the precharge control signal and a source signal; and a word line control section suitable for controlling activation of a program word line and a read word line for performing the program and read operations in response to the word line control signal, wherein the control signal generation section controls the word line control signal to be activated after a predetermined time from the activation of the precharge control signal.Type: ApplicationFiled: June 2, 2017Publication date: April 19, 2018Inventor: Jeong-Tae HWANG