Abstract: A semiconductor device includes a fuse array section suitable for performing program and read operations; a control signal generation section suitable for generating a precharge control signal and a word line control signal; a bit line control section suitable for controlling a precharge operation of a bit line in response to the precharge control signal and a source signal; and a word line control section suitable for controlling activation of a program word line and a read word line for performing the program and read operations in response to the word line control signal, wherein the control signal generation section controls the word line control signal to be activated after a predetermined time from the activation of the precharge control signal.

Abstract: An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.

Abstract: A semiconductor memory device includes: a high frequency signal control unit for receiving an external command address signal, removing noise and glitch from the external command address signal and outputting a first command address signal; a pulse width control unit for controlling a pulse width of the first command address signal or maintaining the pulse width of the first command address signal and outputting a second command address signal with a predetermined pulse width; a refresh operation control unit for generating a row address for a refresh operation in response to the second command address signal; and a memory cell array for performing the a refresh operation in response to the row address.

Abstract: A semiconductor device may be provided. The semiconductor device may include an input signal generator configured to enable an input signal although a reset signal is disabled after a clock enable signal is enabled. The semiconductor device may include a self-refresh enable signal generator configured to generate a self-refresh enable signal based on the input signal.

Abstract: An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs first to (M+1)th command/address signals (wherein, “M” denotes a natural number which is equal to or greater than two) and receives a detection signal to detect a normality/abnormality of a temperature sensor. The second semiconductor device enters a test mode in response to the (M+1)th command/address signal and compare first to Nth sensing codes (wherein, “N” denotes a natural number which is equal to or greater than two) generated by the temperature sensor with the first to Mth command/address signals to generate the detection signal. The second semiconductor device also executes a refresh operation in response to a refresh signal including a plurality of pulses whose cycle time is controlled by the first to Mth command/address signals.

Abstract: A semiconductor system may include a command processor configured to decode a command to generate an active pulse and a delayed active pulse, and a bank active signal generation circuit configured to generate a bank active signal for performing an active operation for a bank accessed by an address. The bank active signal may be disabled in synchronization with the active pulse and is enabled in synchronization with the delayed active pulse.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs commands, a test address, addresses and a precharge signal. The second semiconductor device enters an auto-precharge operation according to a combination of the commands after a read operation or a write operation and receives the test address and the precharge signal to perform an auto-precharge operation of one bank selected from a plurality of banks by the addresses.

Abstract: A memory device may include a plurality of memory banks; a setting circuit capable of setting at least one of an advanced refresh mode and a piled refresh mode; and a refresh control unit capable of controlling the plurality of memory banks into a plurality of groups and for activating the plurality of groups to be refreshed at different times when a refresh command is applied, wherein the refresh control unit divides the memory banks into first groups determined based on the piled refresh mode and refreshes the first groups once, while, in the advanced refresh mode, the refresh control unit divides the memory banks into second groups determined based on the piled refresh mode and additional setting information and refresh the second groups a first number of times, which is more than two and determined based on the additional setting information.

Abstract: A semiconductor system may include a command processor configured to decode a command to generate an active pulse and a delayed active pulse, and a bank active signal generation circuit configured to generate a bank active signal for performing an active operation for a bank accessed by an address. The bank active signal may be disabled in synchronization with the active pulse and is enabled in synchronization with the delayed active pulse.

Abstract: A semiconductor apparatus may include an internal voltage level controller configured to output either a normal trimming code or a test voltage code as a voltage control code in response to a test mode signal, a specific operation start signal, and a specific operation end signal. The semiconductor apparatus may include an internal voltage generator configured to generate an internal voltage and control a voltage level of the internal voltage in response to the voltage control code.

Abstract: A semiconductor apparatus may include an internal voltage level controller configured to output either a normal trimming code or a test voltage code as a voltage control code in response to a test mode signal, a specific operation start signal, and a specific operation end signal. The semiconductor apparatus may include an internal voltage generator configured to generate an internal voltage and control a voltage level of the internal voltage in response to the voltage control code.

Abstract: A semiconductor device including an input unit suitable for transferring external command signals provided from an external device to an internal device and a detection unit suitable for detecting a predetermined command signal among the external command signals, and restricting the transfer of the detected command signal.

Abstract: A semiconductor memory device includes: a normal cell region having normal cells; a redundancy cell region having first redundancy cells replaced with repair target cells of the normal cells and second redundancy cells which are not replaced with the repair target cells; a fuse unit suitable for programming repair information including replacement information and one of state information and a repair address of the repair target cells; a boot-up unit suitable for outputting the repair information programmed in the fuse unit, resetting the repair information in response to a test control signal, and outputting the reset repair information; an information update unit suitable for generating the test control signal; a test control unit suitable for generating a test address during a redundancy test operation; and a test unit suitable for selectively testing the second redundancy cells in response to the test address.

Abstract: A semiconductor integrated circuit device having a function for detecting degradation of a semiconductor device and a method of driving the same are disclosed. The semiconductor integrated circuit device includes an NMOS transistor electrically coupled to a PMOS transistor and configured to constitute an inverter together with the PMOS transistor, a first stress application unit electrically coupled to the PMOS transistor and configured to apply stress to the PMOS transistor, and a second stress application unit electrically coupled to the NMOS transistor and configured to apply the stress to the NMOS transistor.

Abstract: A semiconductor integrated circuit device having a function for detecting degradation of a semiconductor device and a method of driving the same are disclosed. The semiconductor integrated circuit device includes an NMOS transistor electrically coupled to a PMOS transistor and configured to constitute an inverter together with the PMOS transistor, a first stress application unit electrically coupled to the PMOS transistor and configured to apply stress to the PMOS transistor, and a second stress application unit electrically coupled to the NMOS transistor and configured to apply the stress to the NMOS transistor.

Abstract: A semiconductor integrated circuit device may include a target PMOS transistor, a target NMOS transistor, a first stress-applying circuit, a second stress-applying circuit, a third stress-applying circuit and a fourth stress-applying circuit. An inverter may include the target PMOS transistor and the NMOS transistor. The first stress-applying circuit may be configured to apply a first DC level to a gate of the target PMOS transistor. The second stress-applying circuit may be configured to apply a second DC level to a gate of the target NMOS transistor. The third stress-applying circuit may be configured to apply an AC voltage shape to the gate of the target NMOS transistor. The fourth stress-applying circuit may be configured to apply the AC voltage to a drain of the target NMOS transistor.

Abstract: The semiconductor device includes a power control signal generator, a fuse controller and a fuse array portion. The power control signal generator generates a power control signal enabled during a predetermined period from a termination moment of a power-up period and enabled in response to a test mode signal. The fuse controller generates a boot-up signal enabled if a reboot-up signal is inputted during an enablement period of the power control signal. The fuse controller also generates a fuse reset signal enabled if a reset signal is inputted after a clock training operation. The fuse array portion generates a plurality of fuse data initialized if the fuse reset signal is enabled. The plurality of fuse data are programmed according to electrical open/short states of fuses in response to the power control signal.

Abstract: Semiconductor devices are provided. The semiconductor device may include a control signal generator and a fuse array portion. The control signal generator may generate a power control signal, disable the power control signal to a ground voltage signal level during a power-up period, and enable the power control signal to a power supply voltage signal level from a moment that the power-up period terminates until a moment that a mode register set operation terminates. The fuse array portion may execute a boot-up operation while the power control signal is enabled. The fuse array portion may generate fuse data according to an electrical open/short state of a fuse. The fuse may be selected by a level combination of address signals during the boot-up operation.

Abstract: A semiconductor device includes a fuse array for storing normal fuse data and pattern data through a programming operation, a boot-up control unit suitable for generating an enable signal for enabling an output of the pattern data, and a pattern detection unit suitable for detecting a pattern of the pattern data in response to the enable signal, and generating a detection signal. The fuse array outputs the normal fuse data in response to the detection signal.