Abstract: A bank selection circuit includes a command latch unit configured to latch an input command at a time earlier than a rising edge of a clock by a setup time, a command decoder configured to decode a latched command and generate a row operation signal, a bank address latch unit configured to latch an input bank address at a time earlier than the rising edge of the clock by the setup time, a bank address decoder configured to decode a latched bank address and generate a bank selection signal, and a bank selection unit configured to receive the row operation signal and the bank selection signal and transfer the row operation signal to a bank selected by the bank selection signal.

Abstract: A semiconductor memory apparatus may include a bonding pad; a control signal pad; and an operation mode signal generation unit configured to generate a plurality of operation mode signals in response to a bonding signal inputted through the bonding pad and a control signal inputted through the control signal pad.

Abstract: A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.

Abstract: A semiconductor memory device includes first and second bank groups and an internal column address generating circuit. Each of the first and second bank groups includes at least one bank. The internal column address generating circuit converts a column address into a first internal column address and outputs the first internal column address through a first transmission line in response to a bank address if a read operation or a write operation is performed on a bank of the first bank group. Also, the internal column address generating circuit converts the column address into a second internal column address and outputs the second internal column address through a second transmission line in response to the bank address if a read operation or a write operation is performed on a bank of the second bank group.

Abstract: A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system.

Abstract: A shift circuit of a semiconductor device reduces the power consumption of the semiconductor device. The shift circuit comprises a plurality of shifters and a plurality of clock controllers. The plurality of shifters shifts an input signal in sequence in response to a clock. The plurality of clock each supply the clock to a corresponding shifter before an input of the corresponding shifter is activated and stop the supply of the clock to the corresponding shifter when an output of the corresponding shifter is activated.

Abstract: A circuit for controlling precharge in a semiconductor memory apparatus includes a read clock driver configured to drive an internal clock signal and generate a read burst clock signal; a read precharge control unit configured to generate a read auto precharge signal in response to the read burst clock signal, a burst end signal, and a read write mode signal; a write clock driver configured to drive the internal clock signal and generate a write burst clock signal in response to the read write mode signal and a data input off signal; a write precharge control unit configured to generate a write auto precharge signal in response to the write burst clock signal, the burst end signal, a write latency signal, and a write address combination signal; and a precharge signal generation unit configured to combine the read and write auto precharge signals and generate an auto precharge signal.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: A circuit for controlling precharge in a semiconductor memory apparatus includes a read clock driver configured to drive an internal clock signal and generate a read burst clock signal; a read precharge control unit configured to generate a read auto precharge signal in response to the read burst clock signal, a burst end signal, and a read write mode signal; a write clock driver configured to drive the internal clock signal and generate a write burst clock signal in response to the read write mode signal and a data input off signal; a write precharge control unit configured to generate a write auto precharge signal in response to the write burst clock signal, the burst end signal, a write latency signal, and a write address combination signal; and a precharge signal generation unit configured to combine the read and write auto precharge signals and generate an auto precharge signal.

Abstract: A semiconductor memory device is capable of performing a test operation in its various operation modes. Particularly, the semiconductor memory device can enter a test mode in other modes, as well as, an all bank pre-charge mode. The semiconductor memory device includes a test mode control block configured to generate a test signal enabled for a predetermined interval in an active mode, and a mode register set control block configured to enable a mode register set signal for a test operation in the predetermined interval in response to the test signal.

Abstract: A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: A data I/O line control circuit includes a control unit for outputting a control signal after a predetermined time from an activation of a column select signal, and a switching unit for selectively separating a pair of first sub-middle I/O lines, which is coupled to a pair of local I/O lines located at one side of the switching unit, from a pair of second sub-middle I/O lines, which is coupled to both the pair of the local I/O lines and a data bus sense amplifier located at the other side of the switching unit.

Abstract: An apparatus for generating a clock signal of a semiconductor Integrated circuit includes a first clock driver block configured to generate a plurality of first clock signals, a second clock driver block configured to generate a plurality of second clock signals, and a controller configured to stop an operation of at least one of the first clock driver block and the second clock driver block when the semiconductor Integrated circuit is in a predetermined operational state.

Abstract: A data I/O line control circuit includes a control unit for outputting a control signal after a predetermined time from an activation of a column select signal, and a switching unit for selectively separating a pair of first sub-middle I/O lines, which is coupled to a pair of local I/O lines located at one side of the switching unit, from a pair of second sub-middle I/O lines, which is coupled to both the pair of the local I/O lines and a data bus sense amplifier located at the other side of the switching unit.