Abstract: An operation method of a semiconductor memory device including a fuse array for storing one or more repair addresses includes latching additionally a repair address having an address value, which is not stored in the fuse array in response to an active command signal during a repair operation mode, receiving a repair entry control code from an external device in response to a first column command signal during the repair operation mode, performing a rupture operation of the repair address, which is latched, in response to a second column command signal, wherein the rupture operation is determined based on a value of a repair entry control code, and performing exit of the repair operation mode in response to a precharge command signal, which is provided after the second column command signal.

Abstract: An operation method of a semiconductor memory device including a fuse array for storing one or more repair addresses includes latching additionally a repair address having an address value, which is not stored in the fuse array in response to an active command signal during a repair operation mode, receiving a repair entry control code from an external device in response to a first column command signal during the repair operation mode, performing a rupture operation of the repair address, which is latched, in response to a second column command signal, wherein the rupture operation is determined based on a value of a repair entry control code, and performing exit of the repair operation mode in response to a precharge command signal, which is provided after the second column command signal.

Abstract: A semiconductor device including an internal command generator and a bias generator is provided. The internal command generator generates first to fourth internal command signals sequentially enabled in synchronization with pulses of an external program signal. The first internal command signal controls a read operation for reading out data stored in memory cells, and the second and third internal command signals control a program operation for programming the memory cells. The bias generator generates a read bias signal for controlling a level of an output voltage signal, which is applied to an internal circuit, in response to the first and fourth internal command signals.

Abstract: An self-refresh control circuit for controlling a self-refresh operation of a memory device includes a self-refresh control logic block configured to control the memory device to perform the self-refresh operation and an initial refresh control block configured to activate the self-refresh control logic block in an initialization period of the memory device.

Abstract: A bank selection circuit includes a command latch unit configured to latch an input command at a time earlier than a rising edge of a clock by a setup time, a command decoder configured to decode a latched command and generate a row operation signal, a bank address latch unit configured to latch an input bank address at a time earlier than the rising edge of the clock by the setup time, a bank address decoder configured to decode a latched bank address and generate a bank selection signal, and a bank selection unit configured to receive the row operation signal and the bank selection signal and transfer the row operation signal to a bank selected by the bank selection signal.

Abstract: A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.

Abstract: A semiconductor device includes a fuse array for storing normal fuse data and pattern data through a programming operation, a boot-up control unit suitable for generating an enable signal for enabling an output of the pattern data, and a pattern detection unit suitable for detecting a pattern of the pattern data in response to the enable signal, and generating a detection signal. The fuse array outputs the normal fuse data in response to the detection signal.

Abstract: An integrated circuit includes a programmable storage unit suitable for operating with a plurality of powers and outputting stored data in response to a boot-up signal, a register unit suitable for storing the data outputted from the programmable storage unit, a internal circuit suitable for operating by using the data stored in the register unit, a voltage detection unit suitable for activating a power stabilization signal when levels of the plurality of powers are stabilized, and a boot-up control unit suitable for counting a number of activations of a periodic wave from a time of an activation of the power stabilization signal and activating the boot-up signal when the counted number reaches a predetermined number.

Abstract: A semiconductor device including an internal command generator and a bias generator is provided. The internal command generator generates first to fourth internal command signals sequentially enabled in synchronization with pulses of an external program signal. The first internal command signal controls a read operation for reading out data stored in memory cells, and the second and third internal command signals control a program operation for programming the memory cells. The bias generator generates a read bias signal for controlling a level of an output voltage signal, which is applied to an internal circuit, in response to the first and fourth internal command signals.

Abstract: A semiconductor device includes a voltage detection circuit suitable for detecting an external power supply voltage and for sequentially activating first and second power-up signals in a power-up period of the external power supply voltage, and a control circuit suitable for activating at least one first control signal for controlling an internal voltage to be generated based on the first power-up signal, and for activating at least one second control signal for controlling an operation of an internal circuit using the internal voltage when a predetermined time lapses after the first control signal is activated, based on the second power-up signal.

Abstract: A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system.

Abstract: A memory device includes a nonvolatile memory, operated by using a plurality of voltages and configured to output stored repair information in response to a boot-up signal, a plurality of registers configured to store the repair information output from the nonvolatile memory, a plurality of memory banks configured to replace a normal cell with a redundancy cell using the repair information stored in registers corresponding to the plurality of memory banks among the plurality of registers, and a boot-up control circuit configured to activate the boot-up signal at a time of stabilization of the plurality of voltages.

Abstract: A shift circuit of a semiconductor device reduces the power consumption of the semiconductor device. The shift circuit comprises a plurality of shifters and a plurality of clock controllers. The plurality of shifters shifts an input signal in sequence in response to a clock. The plurality of clock each supply the clock to a corresponding shifter before an input of the corresponding shifter is activated and stop the supply of the clock to the corresponding shifter when an output of the corresponding shifter is activated.

Abstract: A semiconductor memory apparatus may include a bonding pad; a control signal pad; and an operation mode signal generation unit configured to generate a plurality of operation mode signals in response to a bonding signal inputted through the bonding pad and a control signal inputted through the control signal pad.

Abstract: A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.

Abstract: A semiconductor memory device is capable of performing a test operation in its various operation modes. Particularly, the semiconductor memory device can enter a test mode in other modes, as well as, an all bank pre-charge mode. The semiconductor memory device includes a test mode control block configured to generate a test signal enabled for a predetermined interval in an active mode, and a mode register set control block configured to enable a mode register set signal for a test operation in the predetermined interval in response to the test signal.

Abstract: An self-refresh control circuit for controlling a self-refresh operation of a memory device includes a self-refresh control logic block configured to control the memory device to perform the self-refresh operation and an initial refresh control block configured to activate the self-refresh control logic block in an initialization period of the memory device.

Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

Abstract: A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.

Abstract: A method of testing a semiconductor memory apparatus is provided. The data alignment units other than the one data align unit being tested are deactivated. Serial data is input to the activated data alignment unit to generate parallel data. The parallel data is decoded. A test mode signal corresponding to the decoded result is enabled to perform the test. Different serial data is input where the test mode signal is enabled to generate and decode parallel data. Both tests are then performed simultaneously based on a test mode signal corresponding to a result of the decoded parallel data.