Abstract: A video decoder may be configured to receive a first instance of a flag for a first block, with a first value for the flag indicating that a cross-component prediction (CCP) mode is derived without signaling and a second value for the flag indicating that the CCP mode is signaled; in response to determining that the first instance of the flag is set to the first value, derive a first CCP mode for the first block; determine a first predicted chroma block for the first block using the first CCP mode; determine a decoded version of the first block based on the first predicted chroma block; and output a picture of decoded video data that includes the decoded version of the first block.

Abstract: A device for decoding encoded video data is configured to determine that a chroma block of the encoded video data is coded in a cross-component prediction (CCP) mode; generate a merge candidate list for the chroma block, wherein the merge candidate list includes at least two prediction candidates generated by different CCP modes and a third prediction candidate, wherein the third prediction candidate comprises a fusion prediction candidate; receive, in the encoded video data, a syntax element set to a value; select a prediction candidate from the merge candidate list based on the value of the syntax element; determine a prediction block for the chroma block based on the selected prediction candidate; determine a decoded block of video data based on the prediction block for the chroma block; and output a decoded picture of video data that includes the decoded block of video data.

Abstract: A semiconductor processing chamber may include a pedestal configured to support a substrate during a plasma-enhanced chemical-vapor deposition (PECVD) process that forms a film on a surface of the substrate. The chamber may also include one or more internal meshes embedded in the pedestal. The one or more internal meshes may be configured to deliver radio-frequency (RF) power to a plasma in the semiconductor processing chamber during the PECVD process. An outer diameter of the one or more internal meshes may be less that a diameter of the substrate. The chamber may further include an RF source configured to deliver the RF power to the one more internal meshes. This configuration may reduce arcing within the processing chamber.

Abstract: Some embodiments of the disclosure describe an evaluation system based on analyte data including a memory storing a program, a display, and a processor. In some examples, the processor is configured to: receive analyte data during a predetermined time period from an object to be tested, acquire a plurality of analyte indicators different from each other based on the analyte data, normalize the plurality of analyte indicators to a predetermined range to acquire a plurality of normalized analyte indicators, plot a polygon pattern corresponding to the analyte data during the first time period as a target polygon pattern, plot a polygon pattern corresponding to the analyte data during the second time period as a reference polygon pattern, and take a line segment between a vertex and a center point as an axis, and display the target polygon pattern and the reference polygon pattern.

Abstract: Some embodiments of the disclosure describe an evaluation system based on analyte data including a memory storing a program, a display, and a processor. In some examples, the processor is configured to: receive analyte data during a predetermined time period from an object to be tested, acquire a plurality of analyte indicators different from each other based on the analyte data, normalize the plurality of analyte indicators to a predetermined range to acquire a plurality of normalized analyte indicators, plot a polygon pattern corresponding to the analyte data during the first time period as a target polygon pattern, plot a polygon pattern corresponding to the analyte data during the second time period as a reference polygon pattern, and take a line segment between a vertex and a center point as an axis, and display the target polygon pattern and the reference polygon pattern.

Abstract: An apparatus and a method for neural network computation are provided. The apparatus for neural network computation includes a first neuron circuit and a second neuron circuit. The first neuron circuit is configured to execute a neural network computation of at least one computing layer with a fixed feature pattern in a neural network algorithm. The second neuron circuit is configured to execute the neural network computation of at least one computing layer with an unfixed feature pattern in the neural network algorithm. The performance of the first neuron circuit is greater than that of the second neuron circuit.

Abstract: A method for preparing high-density magnesia-alumina spinel ceramic by low-temperature pressureless sintering, comprises: using MgAl2O4 powder as a raw material powder, adding calcium phosphate as a sintering aid and controlling the calcium element of the calcium phosphate to not exceed 500 ppm of the total mass of the raw material powder; and then performing pressureless sintering, thereby preparing a high-density magnesia-alumina spinel ceramic; the pressureless sintering includes normal pressure sintering or vacuum sintering.

Abstract: A light emitting diode package structure and a method for manufacturing the same are provided. The LED package structure includes a substrate having a first and a second surface opposite to each other, a conductive structure including a first and a second conductive structure electrically connected with each other, a first gold layer disposed on the first conductive structure, a second gold layer disposed on the second conductive structure, an LED chip disposed on the first gold layer, and a package layer disposed on the first surface and encapsulating the first conductive structure, the first gold layer, and the LED chip. The first conductive structure is disposed on the first surface. The second conductive structure is disposed on the second surface. A thickness of the first gold layer is greater than 1 ?m. The second conductive structure is completely covered by the second gold layer.

Abstract: An insertion slot connector and a connector assembly. The insertion slot connector includes an insulating body and multiple conductive terminals. The insulating body includes two side walls, a bottom wall and an insertion slot. The insulating body has a mating surface and a mounting surface provided opposite to each other. The insertion slot runs through the mating surface. Each conductive terminal includes a base, an elastic arm extending from the base toward the mating surface and turns back to extend toward the bottom wall, a contact portion provided at a tail end of the elastic arm and a soldering portion. A distance between the insertion slot and the soldering surface of the soldering portion in the insertion direction is not greater than 0.70 mm. The connector assembly includes a circuit board and at least one insertion slot connector and at least one card edge connector alternately mounted thereon.

Abstract: The present disclosure provides a driving module and a display device. The driving module includes a serial-parallel conversion circuit and a data providing circuit, the serial-parallel conversion circuit is configured to convert a serial input signal into a parallel output signal and generate a transmission control signal and a common electrode voltage signal in accordance with mode indication information carried by the parallel output signal, and the parallel output signal carries the mode indication information and input display data; and the data providing circuit is configured to convert the input display data into output display data and transmit the output display data to a corresponding data line under the control of the transmission control signal. According to the embodiments of the present disclosure, it is able to achieve display through relying on serial input signals and other signals provided by a system without a display chip.

Abstract: An all-oxide transistor structure includes a substrate, a first transistor, a second transistor, a third transistor and a fourth transistor. The substrate has an upper surface. The first transistor is disposed on the upper surface of the substrate. The second transistor is disposed on the upper surface of the substrate, wherein the second transistor is electrically connected to the first transistor. The third transistor is electrically connected to the second transistor and overlapped with the second transistor in a first direction, wherein the first direction is parallel to a normal direction of the upper surface of the substrate. The fourth transistor is disposed on the upper surface of the substrate, wherein the fourth transistor is electrically connected to the first transistor, the second transistor and the third transistor.

Abstract: A method and system for regulating a multi-component power distribution network with high proportion of distributed power sources.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A circuit board structure is provided. The circuit board structure includes a substrate, a solder mask coupler, a supporter, and a chip. The substrate has a conductive structure. The solder mask coupler is disposed on the substrate. The supporter contacts the solder mask coupler, and the supporter is fixed on the substrate via the solder mask coupler. The chip is disposed on the substrate, and the chip is electrically connected with the conductive structure.

Abstract: The present disclosure describes methods, system, and devices for controlling transmission power. One method includes performing, by a user equipment (UE), transmission power control for uplink (UL) transmission by: receiving, by the UE, a message corresponding to the transmission power control; determining, by the UE, a power control parameter according to the message; and transmitting, by the UE, the UL transmission with a transmission power according to the power control parameter. Another method includes configuring, by a base station, transmission power control for UL transmission by: transmitting, by the base station to a UE, a message corresponding to the transmission power control, so that the UE is configured to determine a power control parameter according to the message; and receiving, by the base station from the UE, the UL transmission with a transmission power according to the power control parameter.

Abstract: The present disclosure describes methods, system, and devices for configuring measurement subband configuration for interference measurement and reporting. One method includes determining, by a user equipment (UE), a measurement subband (MSB) configuration for interference measurement and reporting, the MSB configuration comprising at least one of size information and division information of a plurality of MSBs in a frequency range, the frequency range comprising an uplink (UL) subband; and transmitting, by the UE, feedback information to a base station, the feedback information comprising measurement result for at least one MSB in the plurality of MSBs. Another method includes receiving, by a base station from a UE, an MSB configuration; and receiving, by the base station, feedback information from the UE.

Abstract: A method includes obtaining a plurality of training samples that each include a respective speech utterance and a respective textual utterance representing a transcription of the respective speech utterance. The method also includes fine-tuning, using quantization and sparsity aware training with native integer operations, a pre-trained automatic speech recognition (ASR) model on the plurality of training samples. Here, the pre-trained ASR model includes a plurality of weights and the fine-tuning includes pruning one or more weights of the plurality of weights using a sparsity mask and quantizing each weight of the plurality of weights based on an integer with a fixed-bit width. The method also includes providing the fine-tuned ASR model to a user device.

Abstract: The method for forming the semiconductor structure includes the following steps. A substrate that is divided into a cell region and a peripheral region is provided. A bottom dielectric layer is formed on the substrate. A first stacked structure and a second stacked structure are formed on the bottom dielectric layer. The first stacked structure is disposed in the cell region and the second stacked structure is disposed in the peripheral region. The first stacked structure is patterned to form first conductive stacks. A first cleaning process is performed. A first repair dielectric layer is formed on the first conductive stacks, the second stacked structure, and the bottom dielectric layer. The second stacked structure is patterned to form second conductive stacks. A second cleaning process is performed. A second repair dielectric layer is formed on the first conductive stacks, the second conductive stacks, and the bottom dielectric layer.

Abstract: A ceramic substrate and a method for manufacturing the same are provided. The ceramic substrate includes a spheroidal aluminum nitride powder, a plate-shaped aluminum nitride powder, a boron nitride powder, and an yttrium oxide powder. A percentage by weight of the spheroidal aluminum nitride powder ranges between 63% and 90%. A percentage by weight of the plate-shaped aluminum nitride powder ranges between 0.05% and 30%. A percentage by weight of the boron nitride powder ranges between 0.05% and 2%. A percentage by weight of the yttrium oxide powder ranges between 0.05% and 5%. The method includes a tape casting operation and a primary and pressureless sintering process.

Abstract: An application-level memory control group of a first application may be created when the first application is opened. An anonymous page of the first application is added to a least recently used linked list of the application-level memory control group, and a file page of the first application is added to a global least recently used linked list. An application-level memory control group is created in a dimension of an application, and an anonymous page of the application is managed in a refined manner. In addition, a file page of the application-level memory control group may be managed based on a global least recently used linked list.