Abstract: In a method of manufacturing a semiconductor device, a lower conductive layer is formed in an opening formed in a dielectric layer, and the lower conductive layer is recessed to form a space. A blanket conductive layer is formed over the recessed lower conductive layer in the space, a sidewall of the space and an upper surface of the dielectric layer. Part of the blanket conductive layer formed on the sidewall of the opening and the upper surface of the dielectric layer is removed, thereby forming a upper conductive layer on the lower conductive layer, and a cap insulating layer is formed over the upper conductive layer in the space. The blanket conductive layer is formed by physical vapor deposition.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a first inter-layer dielectric (ILD) layer formed over the fin structure. The FinFET device structure includes a gate structure formed in the first ILD layer, and a first S/D contact structure formed in the first ILD layer and adjacent to the gate structure. The FinFET device structure also includes a first air gap formed on a sidewall of the first S/D contact structure, and the first air gap is in direct contact with the first ILD layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate dielectric layer over a substrate. The method includes forming a work function metal layer over the gate dielectric layer. The method includes forming a glue layer over the work function metal layer. The glue layer is thinner than the gate dielectric layer. The method includes forming a gate electrode over the glue layer. The gate electrode includes fluorine. The method includes annealing the gate electrode. The fluorine diffuses from the gate electrode into the gate dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a cap layer over the gate stack. The semiconductor device structure includes a protective layer over the cap layer, wherein a lower portion of the protective layer extends into the cap layer. The semiconductor device structure includes a contact structure passing through the protective layer and the cap layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a first semiconductor stack and a second semiconductor stack over a substrate, wherein each of the first and second semiconductor stacks includes semiconductor layers stacked up and separated from each other; a dummy spacer between the first and second semiconductor stacks, wherein the dummy spacer contacts a first sidewall of each semiconductor layer of the first and second semiconductor stacks; and a gate structure wrapping a second sidewall, a top surface, and a bottom surface of each semiconductor layer of the first and second semiconductor stacks.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: An identification system of circulating biomarkers for cancer detection, a development method of circulating biomarkers for cancer detection, a cancer detection method and a kit are provided in the present disclosure, and the development method includes the following steps. Expression levels of multiple genes in normal tissue samples and tumor tissue samples are identified, and genes with high expression levels in the tumor tissue samples are selected. Afterwards, a weight of each human tissue’s contribution to plasma exosomes is calculated using tissue-specific genes and group-enriched genes. Next, expression levels of plasma exosome genes of healthy people and cancer patients are compared by an overlapping index, and circulating biomarkers and combinations thereof suitable for detection and evaluation of plasma exosomes are selected.

Abstract: A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.

Abstract: An electrical stimulation method is provided in the present disclosure. The electrical stimulation method is applied to an electrical stimulation device. The electrical stimulation method includes the steps of using the electrical stimulation device to obtain an electrical stimulation level, wherein the electrical stimulation level corresponds to the target energy; and using the electrical stimulation device to perform the electrical stimulation on the target area of a target object according to the target energy, wherein during the electrical stimulation, all electrodes of the electrical stimulation device are activated.

Abstract: An impedance monitoring method is applied to a non-implantable electrical stimulation device including an electrical stimulator and an electrode assembly. The electrical stimulator is detachably electrically connected to the electrode assembly, and stores the impedance values of the electrical stimulator and the electrode assembly. The impedance monitoring method includes the following steps. The electrical stimulator generates an electrical stimulation signal. The electrical stimulation signal performs electrical stimulation of a target area through the electrode assembly. The electrical stimulator samples the electrical stimulation signal to calculate the total impedance value corresponding to the electrical stimulation signal. The electrical stimulator calculates the tissue impedance value according to the total impedance value, the impedance value of the electrical stimulator, and the impedance value of the electrode assembly.

Abstract: An electrical stimulation method for impedance compensation is applied to a non-implantable electrical stimulation device that provides high-frequency electrical stimulation. The non-implantable electrical stimulation device includes an electrical stimulator and an electrode assembly. The electrical stimulator is detachably electrically connected to the electrode assembly. The electrical stimulation method for impedance compensation includes the following steps. A high-frequency environment is provided and the first impedance value of the electrode assembly is calculated according to at least one of the measured first resistance value, first capacitance value, or first inductance value of the electrode assembly. The high-frequency environment is provided and the second impedance value of the electrical stimulator is calculated according to at least one of the measured second resistance value, second capacitance value, or second inductance value of the electrical stimulator.

Abstract: An electrical stimulation method for impedance compensation is provided. The electrical stimulation method for impedance compensation is applied to an electrical stimulation device for providing high frequency electrical stimulation. In the above method, by an impedance compensation device, a high-frequency environment is provided and a first impedance value of a lead is calculated according to at least one of a measured first resistance value, a measured first capacitance value and a measured first inductance value of the lead is calculated. By the impedance compensation device, the high-frequency environment is provided and a second impedance value of the electrical stimulation device is calculated according to at least one of a measured second resistance value, a measured second capacitance value and a measured second inductance value of the electrical stimulation device. The first impedance value and the second impedance value are stored for calculating a tissue impedance.

Abstract: An electrical stimulation method is provided. The electrical stimulation method is applied to an electrical stimulation device and an external control device. The electrical stimulation method includes the following steps. The predetermined electrical stimulation level that corresponds to the predetermined target energy is obtained by the external control device. The predetermined target energy is one of the target energies in the first target energy set. The external control device selects the target energy upper bound and the target energy lower bound from the first target energy set according to the predetermined electrical stimulation level. The external control device generates a second target energy set according to the target energy upper bound and the target energy lower bound. The electrical stimulation device performs electrical stimulation of the target area of a target object according to the second target energy set.

Abstract: An electrical stimulation method is provided. The electrical stimulation method is applied to an electrical stimulation device. The steps of the electrical stimulation method include obtaining a target energy value; providing an electrical stimulation signal to a target area; calculating a total energy value according to an energy value transmitted from the electrical stimulation signal to the target area; and determining whether the total energy value has reached the target energy value.

Abstract: An electrical stimulation method is provided in the disclosure. The electrical stimulation method is applied to a non-implantable electrical stimulation device, wherein the non-implantable electrical stimulation device includes an electrical stimulator and an electrode assembly. The electrical stimulator is detachably electrically connected to the electrode assembly. The electrical stimulation method includes the following steps. The electrical stimulator provides an electrical stimulation signal. The electrical stimulation signal is transmitted to a target area through the electrode assembly. The total energy value is calculated according to the energy value of the electrical stimulation signal.

Abstract: An impedance-monitoring method, applied to an electrical-stimulation device and a lead, is provided. The electrical-stimulation device stores a first impedance value of the electrical-stimulation device and a second impedance value of the lead. The method includes the following steps: utilizing the electrical-stimulation device to generate an electrical-stimulation signal, and to perform electrical stimulation on a target area using the electrical-stimulation signal; utilizing the electrical-stimulation device to sample the electrical-stimulation signal to calculate a total impedance value corresponding to the electrical-stimulation signal; and utilizing the electrical-stimulation device to calculate a tissue-impedance value according to the total impedance value, the first impedance value of the electrical-stimulation device, and the second impedance value of the lead. The tissue-impedance value is used to calculate the energy value of the electrical-stimulation signal transmitted to the target area.

Abstract: An electrical stimulation method for determining the quality of an electrical-stimulation signal is provided in the invention. The electrical stimulation method is adapted for use in an electrical-stimulation device for performing an electrical stimulation. The electrical stimulation method may include the steps of generating the electrical-stimulation signal; sampling the electrical-stimulation signal; performing a fast Fourier transform on the sampled electrical-stimulation signal; and determining whether the signal quality of the electrical-stimulation signal on which the fast Fourier transform was performed meets a threshold.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: A semiconductor device includes a stack of semiconductor layers vertically arranged above a semiconductor base structure, a gate dielectric layer having portions each surrounding one of the semiconductor layers, and a gate electrode surrounding the gate dielectric layer. Each portion of the gate dielectric layer has a top section above the respective semiconductor layer and a bottom section below the semiconductor layer. The top section has a top thickness along a vertical direction perpendicular to a top surface of the semiconductor base structure; and the bottom section has a bottom thickness along the vertical direction. The top thickness is greater than the bottom thickness.