Abstract: The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a first channel members being vertically stacked, a second channel members being vertically stacked, an n-type work function layer wrapping around each of the first channel members, a first p-type work function layer over the n-type work function layer and wrapping around each of the first channel members, a second p-type work function layer wrapping around each of the second channel members, a third p-type work function layer over the second p-type work function layer and wrapping around each of the second channel members, and a gate cap layer over a top surface of the first p-type work function layer and a top surface of the third p-type work function layer such that the gate cap layer electrically couples the first p-type work function layer and the third p-type work function layer.

Abstract: The present disclosure provides an electrical stimulation device. The electrical stimulation device includes a signal receiving circuit and a signal processing circuit. The signal receiving circuit receives and outputs a frequency signal. The signal processing circuit receives the frequency signal and provides an electrical stimulation signal according to the frequency signal.

Abstract: An electrical stimulation device includes a signal receiving circuit, a rectifying circuit and a signal processing circuit. The signal receiving circuit receives and outputs a frequency signal. The rectifying circuit receives the frequency signal and rectifies the frequency signal to generate a rectifying signal. The signal processing circuit receives the rectifying signal to generate an electrical stimulation signal.

Abstract: A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.

Abstract: A semiconductor device includes stacks of nano-structures that each extend in a first horizontal direction. The stacks each extend in a vertical direction and are separated from one another in a second horizontal direction. A first gate is disposed over a first subset of the stacks. A second gate is disposed over a second subset of the stacks. A first conductive capping layer is disposed over a substantial entirety of an upper surface of the first gate. A second conductive capping layer is disposed over a substantial entirety of an upper surface of the second gate. A dielectric structure is disposed between the first gate and the second gate in the second horizontal direction. The dielectric structure physically and electrically separates the first gate and the second gate. An upper surface of the dielectric structure is substantially free of having the first or second conductive capping layers disposed thereon.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming an n-type work function layer in a gate trench in a gate structure, wherein the n-type work function layer is formed around first channel layers in a p-type gate region and around second channel layers in an n-type gate region, forming a first metal fill layer in a first gate trench over the n-type work function layer in the p-type gate region and in a second gate trench over the n-type work function layer in the n-type gate region, removing the first metal fill layer from the p-type gate region, removing the n-type work function layer from the p-type gate region, forming a p-type work function layer in the first gate trench of the p-type gate region, and forming a second metal fill layer in the first gate trench of the p-type gate region.

Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, an exemplary semiconductor structure includes a gate structure. The gate structure includes a gate dielectric layer, an n-type work function layer embedded in the gate dielectric layer, a dielectric capping layer embedded in the n-type work function layer, and a p-type work function layer embedded in the dielectric capping layer. A top surface of the gate structure exposes the n-type work function layer, the dielectric capping layer, and the p-type work function layer. The semiconductor structure also includes a first metal cap on the n-type work function layer and a second metal cap on the p-type work function layer. The first metal cap is spaced apart from the second metal cap. without formed on the dielectric capping layer.

Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a first inter-layer dielectric (ILD) layer formed over the fin structure. The FinFET device structure includes a gate structure formed in the first ILD layer, and a first S/D contact structure formed in the first ILD layer and adjacent to the gate structure. The FinFET device structure also includes a first air gap formed on a sidewall of the first S/D contact structure, and the first air gap is in direct contact with the first ILD layer.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

Abstract: A semiconductor device includes a stack of semiconductor layers vertically arranged above a semiconductor base structure, a gate dielectric layer having portions each surrounding one of the semiconductor layers, and a gate electrode surrounding the gate dielectric layer. Each portion of the gate dielectric layer has a top section above the respective semiconductor layer and a bottom section below the semiconductor layer. The top section has a top thickness along a vertical direction perpendicular to a top surface of the semiconductor base structure; and the bottom section has a bottom thickness along the vertical direction. The top thickness is greater than the bottom thickness.

Abstract: A semiconductor device includes an interface layer on a substrate, a gate dielectric layer on the interface layer, and a work function metal layer on the gate dielectric layer. An interface between the interface layer and the gate dielectric layer has a concentration of a dipole-inducing element. The semiconductor device also includes an oxygen blocking layer on the work function metal layer and a metal fill layer on the oxygen blocking layer.

Abstract: A transistor is provided. The transistor includes a first source/drain epitaxial feature, a second source/drain epitaxial feature, and two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature. The two or more semiconductor layers comprise different materials. The transistor further includes a gate electrode layer surrounding at least a portion of the two or more semiconductor layers, wherein the transistor has two or more threshold voltages.

Abstract: A method includes receiving a workpiece having a first stack of semiconductor layers in a first region and a second stack of semiconductor layers in a second region; forming a first gate dielectric layer surrounding each layer of the first stack and a second gate dielectric layer surrounding each layer of the second stack; forming a first dipole layer surrounding the first gate dielectric layer and merging between vertically adjacent portions of the first gate dielectric layer, and a second dipole layer surrounding the second gate dielectric layer and merging between vertically adjacent portions of the second gate dielectric layer; removing the first dipole layer; after the removing of the first dipole layer, conducting a first annealing on the workpiece; removing a remaining portion of the second dipole layer; and forming a gate electrode layer in the first region and the second region.

Abstract: A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.

Abstract: A semiconductor device includes a plurality of active region structures that each protrude upwards in a vertical direction. The active region structures each extend in a first horizontal direction. The active region structures are separated from one another in a second horizontal direction different from the first horizontal direction. A gate structure is disposed over the active region structures. The gate structure extends in the second horizontal direction. The gate structure partially wraps around each of the active region structures. A conductive capping layer is disposed over the gate structure. A gate via is disposed over the conductive capping layer. A dimension of the conductive capping layer measured in the second horizontal direction is substantially greater than a maximum dimension of the gate via measured in the second horizontal direction.