Abstract: A semiconductor device contact structure practically eliminating the copper diffusion into the solder as well as the current crowding at the contact with the subsequent electromigration in the solder. A column-like electroplated copper stud (108) is on each contact pad. The stud is sized to provide low, uniform electrical resistance in order to spread the current from the contact to an approximately uniform, low density. Preferably, the stud height (108a) is at least ten times the thickness of the copper interconnect layer (104). Stud (108) is capped by an electroplated nickel layer (109) thick enough (preferably about 2 ?m) to suppress copper diffusion from stud (108) into solder body (120), thus practically inhibiting intermetallic compound formation and Kirkendall voiding.

Abstract: A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure (11) having a stiff structural component (501, 502) positioned above and affixed to a conductive metal pad (103) formed in a last metal layer (104). The die test structure (11) may also include a dedicated support structure (41) below the conductive metal pad which includes a predetermined pattern of metal lines formed in the interconnect layers (18, 22, 26). After mounting the integrated circuit in a test device, a shear knife (601) is positioned for lateral movement to cause the shear knife to contact the stiff structural component (501). Any damage to the die test structure caused by the lateral movement of the shear knife may be assessed to evaluate the mechanical integrity of the interconnect stack.

Abstract: A method of forming an embedded device build-up package (10) includes forming a first plurality of features (22) over a packaging substrate (12,16,18), wherein the first plurality of features (22) comprises a first feature and a second feature, forming at least a first crack arrest feature (28) in a first crack arrest available region (26), wherein the first crack arrest available region is between the first feature and the second feature, forming a second plurality of features (32) over the first plurality of features (22) wherein the second plurality of features includes a third feature and a fourth feature, and forming at least a second crack arrest feature (36) in a second crack arrest available region (34), wherein the second crack arrest feature (36) is between the third feature and the fourth feature, and the second crack arrest feature (36) is substantially orthogonal to the first crack arrest feature (28).

Abstract: A semiconductor device contact structure practically eliminating the copper diffusion into the solder as well as the current crowding at the contact with the subsequent electromigration in the solder. A column-like electroplated copper stud (108) is on each contact pad. The stud is sized to provide low, uniform electrical resistance in order to spread the current from the contact to an approximately uniform, low density. Preferably, the stud height (108a) is at least ten times the thickness of the copper interconnect layer (104). Stud (108) is capped by an electroplated nickel layer (109) thick enough (preferably about 2 ?m) to suppress copper diffusion from stud (108) into solder body (120), thus practically inhibiting intermetallic compound formation and Kirkendall voiding.

Abstract: A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device may be placed on a conductive layer such that an active surface of circuit device is between conductive layer and an opposite surface of circuit device. The conductive layer has at least one opening to expose the active surface of circuit device. The encapsulant may be electrically conductive or electrically non-conductive.

Abstract: A semiconductor device (100) with a metal bump (203) on each interior contact pad (202) has a metallic leadframe with lead segments (220) with the first surface (220a) in one plane. The second surface (220b) is castellated across the segment width in two planes so that regions of a first segment thickness (240a) alternate with regions of a reduced (about 50%) second segment thickness (240b); the first thickness regions are in the locations corresponding to the chip interior contact pads (half-etched leadframe). The second segment surface faces the chip so that each first thickness region aligns with the corresponding chip bump. The chip bumps are attached to the corresponding second segment surface using reflow metal. Dependent on the orientation of the attached half-etched segment, thermomechanical stress concentrations away shift from the solder joints into the leadframe metal, or shear stress may reduced.

Abstract: In a method and system for fabricating a semiconductor device (200, 300 or 400), a portion of a metal sheet to form a leadframe (210, 310 or 410) having a lead finger (220, 320 or 430) is removed to form a lead finger lock (260, 360 or 460). The lead finger lock (260, 360 or 460) is disposed within a configurable distance of a wirebonding joint (240, 340 or 440) located on a surface of the lead finger (220, 320 or 430). An integrated circuit (IC) chip (290, 390 or 490) is attached to the leadframe (210, 310 or 410). A conductive pad end (232, 332 or 432) of a bond wire (230, 330 or 430) is bonded to the IC chip (290, 390 or 490) and a lead finger end (234, 334 or 434) of the bond wire is bonded to an inner end (222, 322 or 422) of the lead finger at the wirebonding joint (240, 340 or 440). The IC chip, the leadframe, the lead finger, and the wirebonding are encapsulated with a molding compound (MC) (250, 350 or 450).

Abstract: A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device (115) may be placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). The conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive or electrically non-conductive.

Abstract: A method of forming an embedded device build-up package (10) includes forming a first plurality of features (22) over a packaging substrate (12,16,18), wherein the first plurality of features (22) comprises a first feature and a second feature, forming at least a first crack arrest feature (28) in a first crack arrest available region (26), wherein the first crack arrest available region is between the first feature and the second feature, forming a second plurality of features (32) over the first plurality of features (22) wherein the second plurality of features includes a third feature and a fourth feature, and forming at least a second crack arrest feature (36) in a second crack arrest available region (34), wherein the second crack arrest feature (36) is between the third feature and the fourth feature, and the second crack arrest feature (36) is substantially orthogonal to the first crack arrest feature (28).

Abstract: A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Abstract: A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure (11) having a stiff structural component (501, 502) positioned above and affixed to a conductive metal pad (103) formed in a last metal layer (104). The die test structure (11) may also include a dedicated support structure (41) below the conductive metal pad which includes a predetermined pattern of metal lines formed in the interconnect layers (18, 22, 26). After mounting the integrated circuit in a test device, a shear knife (601) is positioned for lateral movement to cause the shear knife to contact the stiff structural component (501). Any damage to the die test structure caused by the lateral movement of the shear knife may be assessed to evaluate the mechanical integrity of the interconnect stack.

Abstract: A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Abstract: A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device (115) may be placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). The conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive or electrically non-conductive.

Abstract: A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device (115) may be placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). The conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126,326) may be electrically conductive or electrically non-conductive.

Abstract: In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.

Abstract: In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.

Abstract: In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.