Patents by Inventor Jie Lin
Jie Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12362557Abstract: Systems and methods are provided for a self-biasing electro-static discharge (ESD) power clamp. The ESD power clamp comprises an ESD detection circuit coupled to a positive supply voltage node and a ground voltage node. The ESD detection circuit includes a first node having a first voltage level during a standby mode and a second voltage level during an ESD mode. The ESD power clamp further comprises a discharge circuit coupled to the ESD detection circuit that includes a plurality of discharge elements a self-biasing node having a third voltage level during the standby mode. The third voltage level provides a voltage drop across at least one of the discharge elements that is less than the first voltage level. The discharge circuit provides a high-impedance path during the standby mode and a low-impedance path during the ESD mode.Type: GrantFiled: March 31, 2023Date of Patent: July 15, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tao Yi Hung, Jam-Wem Lee, Kuo-Ji Chen, Wun-Jie Lin
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Patent number: 12356729Abstract: A snapback electrostatic discharge (ESD) protection circuit includes a first well in a substrate, a drain region of a transistor, a source region of the transistor, a gate region of the transistor, and a second well embedded in the first well. The first well has a first dopant type. The drain region is in the first well, and has a second dopant type different from the first dopant type. The source region is in the first well, has the second dopant type, and is separated from the drain region in a first direction. The gate region is over the first well and the substrate. The second well is embedded in the first well, and is adjacent to a portion of the drain region. The second well has the second dopant type.Type: GrantFiled: January 7, 2021Date of Patent: July 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Lin Hsu, Yu-Hung Yeh, Yu-Ti Su, Wun-Jie Lin
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Publication number: 20250215902Abstract: A handheld fan comprises a mesh grid assembly, a motor, and fan blades, wherein the mesh grid assembly comprises a front mesh component and a rear mesh component, the front mesh component and the rear mesh component are fixedly combined with each other, at least one portion of the front mesh component extends in a direction away from the rear mesh component, and at least one portion of the rear mesh component extends in a direction away from the front mesh component; the motor is accommodated between the front mesh component and the rear mesh component, and the motor drives the fan blades to rotate between the front mesh component and the rear mesh component.Type: ApplicationFiled: October 4, 2024Publication date: July 3, 2025Applicant: Shenzhen Youwei Technology Co., LtdInventors: Xuegang TAN, Jie LIN
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Publication number: 20250219031Abstract: The invention provides a semiconductor structure, which comprises a first substrate and a second substrate stacked with each other. A first passive element is located in the first substrate and a second passive element is located in the second substrate. A first wire layer is located on a top surface of the first substrate and electrically connected with the first passive element, and a conductive pad is located on a bottom surface of the second substrate and directly contacts the first wire layer.Type: ApplicationFiled: January 3, 2024Publication date: July 3, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Feng Hsu, Shing-Ren Sheu, Kai-Kuang Ho, Yu-Jie Lin
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Publication number: 20250207651Abstract: The vibration damping system includes a vibration damping device on a processing machine and a control unit. The vibration damping device includes a base, a rigid module, a drive module, a counterweight module and a damping module disposed on the counterweight module. The rigid module includes a holder, a guide bar connected to the holder and a moving member disposed on the guide bar. The drive module drives the moving member to move along a first axis. The counterweight module includes a guider and a counterweight mass unit movable along a second axis through the guider. The control unit controls the processing machine and controls the drive module to change a position of the moving member along the first axis according to a vibration frequency of the processing machine in real time, so that vibration frequencies of the vibration damping device and the processing machine are matched.Type: ApplicationFiled: March 18, 2024Publication date: June 26, 2025Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Jheng-Jie LIN, Hsiao-Chen HO, Chien-Chih LIAO
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Publication number: 20250198930Abstract: The present disclosure provides a multifunctional composite bioprobe and a preparation method and use thereof. The multifunctional composite bioprobe includes one or more of noble metal SERS bioprobes and one or more of magnetic semiconductor SERS bioprobes. According to the present disclosure, the functional superposition of the noble metal SERS bioprobe and the magnetic semiconductor SERS bioprobe is realized through the simplest and most effective way, which improves the sensitivity and accuracy of the detection method, and endows magnetic enrichment characteristics for the detection method.Type: ApplicationFiled: March 17, 2023Publication date: June 19, 2025Inventors: Aiguo WU, Jie LIN, Xiaoxia WU, Guoliang SHAO, Dinghu ZHANG
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Publication number: 20250146939Abstract: Disclosed are a SERS nano-particle, a preparation method therefor, and an application thereof to a method for distinguishing CTCs from WBCs. The SERS nano-particle are formed by core magnetic particles, noble metal nano-particles, Raman signal molecules, hydrophilic molecules and target molecules. A method for distinguishing CTCs from WBCs comprises: enabling a SERS nano-particle to make contact with a to-be-detected solution containing CTCs and/or WBCs; performing incubation; then detecting SERS signal intensity of a cell combined with the SERS nano-particle; setting SERS signal intensity threshold; if SERS signal intensity of the cell combined with the SERS nano-particle exceeds SERS signal intensity threshold, determining the cell as CTS; otherwise, determining the cell as WBC. A ROC curve is used for the first time to assist the SERS technique in distinguishing CTCs from WBCs.Type: ApplicationFiled: February 15, 2023Publication date: May 8, 2025Inventors: Aiguo WU, Jie LIN, Dinghu Zhang, Xiaoxia WU, Guoliang SHAO
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Publication number: 20250142960Abstract: An array substrate, including: a base; common electrode lead groups in the active area and on a side of the base, where at least one common electrode lead group includes at least one first common electrode lead extending in a first direction, and the common electrode lead groups are arranged in a second direction; and at least one common electrode connection line, which is in the non-active area, on the same side of the base as the first common electrode lead, and extends in the second direction; where a connection group is provided at a position of the common electrode connection line opposite to an end of at least one of the common electrode lead groups, the connection group includes a plurality of connectors, and the number of connectors in the connection group is not less than the number of first common electrode leads in the common electrode lead groups.Type: ApplicationFiled: February 23, 2023Publication date: May 1, 2025Inventors: Xin FANG, Xu XU, Xintong WU, Jie LIN, Lixia ZHANG
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Patent number: 12288503Abstract: A gate driving unit and a driving method for the same, a shift register circuit, and a display apparatus, and an operating period of the gate driving unit comprises a first and a second sub-period; a first pull-down node control module in the gate driving unit causes a first pull-down sub-node to be at an inactive level in the second sub-period, and causes the first pull-down sub-node to be at an active level during a reset phase in the first sub-period; a second pull-down node control module causes a second pull-down sub-node to be at an inactive level in the first sub-period, and causes the second pull-down sub-node to be at an active level during a reset phase in the second sub-period. It is possible to shorten the turn-on time of transistors controlled by the first and the second pull-down sub-nodes, and improve the reliability of the gate driving unit.Type: GrantFiled: May 20, 2024Date of Patent: April 29, 2025Assignee: Xiamen Tianma Optoelectronics Co., Ltd.Inventors: Zongcai Ding, Tianci Li, Weiqiang Wu, Jie Lin, Xiaohe Li, Qiongqin Mao
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Patent number: 12288358Abstract: A method includes: selecting, from among a series of images, a candidate image that was captured at an image-capturing time instant corresponding to a point-cloud-generating time instant at which a point cloud was generated; generating a two-dimensional data set from the point cloud; superimposing the two-dimensional data set on the candidate image to result in a superimposed image; obtaining a derived distance inconsistency between the candidate image and the two-dimensional data set in the superimposed image; feeding the derived distance inconsistency into a conversion model to obtain a derived time difference; calculating a target time instant based on the derived time difference and the image-capturing time instant of the candidate image; and selecting, from among the series of images that have been received from the image capturing device, a target image that was captured at a time instant the closest to the target time instant.Type: GrantFiled: December 2, 2022Date of Patent: April 29, 2025Assignee: Automotive Research & Testing CenterInventors: Wei-Xiang Huang, Yi-Jie Lin
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Publication number: 20250133838Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a first resistance-capacitance (RC) timer circuit, a second RC timer circuit, a voltage pull-down circuit, a voltage pull-up circuit, a discharge circuit, and a discharge control circuit. The first RC timer circuit is coupled between a first power supply voltage and a reference voltage. The second RC timer circuit is coupled between a second power supply voltage and the reference voltage. The voltage pull-up circuit is coupled between the second power supply voltage and the reference voltage through a first resistor. The discharge circuit is coupled between the second power supply voltage and the reference voltage. The discharge control circuit is coupled between a third node and the reference voltage, and controls the discharge circuit using a first voltage generated by the first RC timer circuit.Type: ApplicationFiled: October 19, 2023Publication date: April 24, 2025Inventors: LI-WEI CHU, WUN-JIE LIN
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Publication number: 20250132558Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.Type: ApplicationFiled: October 18, 2023Publication date: April 24, 2025Inventors: LI-WEI CHU, WUN-JIE LIN
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Publication number: 20250125611Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.Type: ApplicationFiled: December 20, 2024Publication date: April 17, 2025Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Li-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
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Publication number: 20250120189Abstract: An optical communication system includes an optical waveguide and a photodetector (PD). The optical waveguide is arranged to receive and guide an optical signal. The PD is configured to receive the optical signal from the optical waveguide and to convert the optical signal into an electrical signal. The PD includes a stack of layers including at least (i) first layers including two or more semiconductor layers forming a reverse-biased semiconductor junction configured to produce the electrical signal in response to the optical signal impinging thereon, and (ii) second layers forming a capacitance component that in is connected with series the reverse-biased semiconductor junction. The PD further includes a first electrode and a second electrode, configured to (i) apply one or more voltages that reverse-bias the reverse-biased semiconductor junction and (ii) output the electrical signal.Type: ApplicationFiled: October 9, 2024Publication date: April 10, 2025Inventors: Hamed Pishvaibazargani, Jie Lin, Masaki Kato
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Publication number: 20250107244Abstract: A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.Type: ApplicationFiled: September 25, 2023Publication date: March 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Chu, Jam-Wem Lee, Wun-Jie Lin, Shou Ming Liu
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Publication number: 20250098304Abstract: A display substrate includes a driving circuit arranged on a base substrate, the driving circuit includes a first node control circuit including a first transistor and a second transistor; a gate/first/second electrode of the first transistor is electrically connected to a first control terminal a first voltage terminal the first node; a gate/first/second electrode of the second transistor is electrically connected to a second control terminal the first node a second voltage terminal; the display substrate also includes a first connection structure and a second connection structure arranged on the base substrate; the first transistor is connected to a part of the first connection structure; and/or, the second transistor is connected to a part of the second connection structure.Type: ApplicationFiled: December 23, 2022Publication date: March 20, 2025Inventors: Xiaolong CHEN, Wenchao WANG, Xin FANG, Sangjin PARK, Jinliang WANG, Jie LIN
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Publication number: 20250098328Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a doped region in the substrate. The semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. The semiconductor device further includes a deep trench isolation (DTI) structure extending through the active area and between the emitter region and the collector region.Type: ApplicationFiled: December 5, 2024Publication date: March 20, 2025Inventors: Tzu-Hao CHIANG, Wun-Jie LIN, Jam-Wem LEE
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Publication number: 20250089379Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.Type: ApplicationFiled: November 26, 2024Publication date: March 13, 2025Inventors: Tao-Yi HUNG, Wun-Jie LIN, Jam-Wem LEE, Kuo-Ji CHEN
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Publication number: 20250082771Abstract: The present disclosure relates to the field of pharmaceutical preparations, dosage regimens, and administration of an antibody-drug conjugate (ADC). More specifically, the ADC is composed of an anti-cadherin-6 (CDH6) antibody connected via a linker to an anticancer agent, such as topoisomerase I inhibitor.Type: ApplicationFiled: November 22, 2024Publication date: March 13, 2025Applicant: DAIICHI SANKYO COMPANY, LIMITEDInventors: Robert Mcleod, Yusuke Myobatake, Tomomichi Ishizaka, Yumi Nishiya, Chiemi Saito, Hirokazu Suzuki, Shotaro Nagase, Thuy Vu Craveiro, Kulandayan Subramanian, Jie Lin, Daigo Asano, Felipe Kellermann Hurtado
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Publication number: 20250072108Abstract: Capacitor cells are provided. A first PMOS transistor has a source connected to a power supply and a drain connected to a first node. A first NMOS transistor has a source connected to a ground and a drain connected to a second node. A second PMOS transistor has a source connected to the second node and a drain connected to the first node. A second NMOS transistor has a source connected to the ground and a drain connected to the first node. A first P+ doped region is shared by drains of the first and second PMOS transistors. A first gate metal is between the first P+ doped region and a second P+ doped region. A first N+ doped region is shared by sources of the first and second NMOS transistors. A second gate metal is between the first N+ doped region and a second N+ doped region.Type: ApplicationFiled: November 12, 2024Publication date: February 27, 2025Inventors: Chien-Yao HUANG, Wun-Jie LIN, Chia-Wei HSU, Yu-Ti SU