Abstract: Disclosed are a SERS nano-particle, a preparation method therefor, and an application thereof to a method for distinguishing CTCs from WBCs. The SERS nano-particle are formed by core magnetic particles, noble metal nano-particles, Raman signal molecules, hydrophilic molecules and target molecules. A method for distinguishing CTCs from WBCs comprises: enabling a SERS nano-particle to make contact with a to-be-detected solution containing CTCs and/or WBCs; performing incubation; then detecting SERS signal intensity of a cell combined with the SERS nano-particle; setting SERS signal intensity threshold; if SERS signal intensity of the cell combined with the SERS nano-particle exceeds SERS signal intensity threshold, determining the cell as CTS; otherwise, determining the cell as WBC. A ROC curve is used for the first time to assist the SERS technique in distinguishing CTCs from WBCs.

Abstract: An array substrate, including: a base; common electrode lead groups in the active area and on a side of the base, where at least one common electrode lead group includes at least one first common electrode lead extending in a first direction, and the common electrode lead groups are arranged in a second direction; and at least one common electrode connection line, which is in the non-active area, on the same side of the base as the first common electrode lead, and extends in the second direction; where a connection group is provided at a position of the common electrode connection line opposite to an end of at least one of the common electrode lead groups, the connection group includes a plurality of connectors, and the number of connectors in the connection group is not less than the number of first common electrode leads in the common electrode lead groups.

Abstract: A gate driving unit and a driving method for the same, a shift register circuit, and a display apparatus, and an operating period of the gate driving unit comprises a first and a second sub-period; a first pull-down node control module in the gate driving unit causes a first pull-down sub-node to be at an inactive level in the second sub-period, and causes the first pull-down sub-node to be at an active level during a reset phase in the first sub-period; a second pull-down node control module causes a second pull-down sub-node to be at an inactive level in the first sub-period, and causes the second pull-down sub-node to be at an active level during a reset phase in the second sub-period. It is possible to shorten the turn-on time of transistors controlled by the first and the second pull-down sub-nodes, and improve the reliability of the gate driving unit.

Abstract: A method includes: selecting, from among a series of images, a candidate image that was captured at an image-capturing time instant corresponding to a point-cloud-generating time instant at which a point cloud was generated; generating a two-dimensional data set from the point cloud; superimposing the two-dimensional data set on the candidate image to result in a superimposed image; obtaining a derived distance inconsistency between the candidate image and the two-dimensional data set in the superimposed image; feeding the derived distance inconsistency into a conversion model to obtain a derived time difference; calculating a target time instant based on the derived time difference and the image-capturing time instant of the candidate image; and selecting, from among the series of images that have been received from the image capturing device, a target image that was captured at a time instant the closest to the target time instant.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a first resistance-capacitance (RC) timer circuit, a second RC timer circuit, a voltage pull-down circuit, a voltage pull-up circuit, a discharge circuit, and a discharge control circuit. The first RC timer circuit is coupled between a first power supply voltage and a reference voltage. The second RC timer circuit is coupled between a second power supply voltage and the reference voltage. The voltage pull-up circuit is coupled between the second power supply voltage and the reference voltage through a first resistor. The discharge circuit is coupled between the second power supply voltage and the reference voltage. The discharge control circuit is coupled between a third node and the reference voltage, and controls the discharge circuit using a first voltage generated by the first RC timer circuit.

Abstract: The present disclosure provides a semiconductor device and an electrostatic discharge (ESD) clamp circuit. The semiconductor device includes a voltage divider, a cascoded inverter, and a discharge circuit. The voltage divider is electrically coupled between a power supply voltage and an output voltage of the semiconductor device. The cascoded inverter is electrically coupled to the voltage divider. The discharge circuit is electrically coupled to the cascoded inverter. The cascoded inverter is configured to turn on the discharge circuit o discharge an electrostatic discharge (ESD) current in response to an ESD event occurring on the power supply voltage or the output voltage when the semiconductor device is in an ESD mode.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Abstract: An optical communication system includes an optical waveguide and a photodetector (PD). The optical waveguide is arranged to receive and guide an optical signal. The PD is configured to receive the optical signal from the optical waveguide and to convert the optical signal into an electrical signal. The PD includes a stack of layers including at least (i) first layers including two or more semiconductor layers forming a reverse-biased semiconductor junction configured to produce the electrical signal in response to the optical signal impinging thereon, and (ii) second layers forming a capacitance component that in is connected with series the reverse-biased semiconductor junction. The PD further includes a first electrode and a second electrode, configured to (i) apply one or more voltages that reverse-bias the reverse-biased semiconductor junction and (ii) output the electrical signal.

Abstract: A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a doped region in the substrate. The semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. The semiconductor device further includes a deep trench isolation (DTI) structure extending through the active area and between the emitter region and the collector region.

Abstract: A display substrate includes a driving circuit arranged on a base substrate, the driving circuit includes a first node control circuit including a first transistor and a second transistor; a gate/first/second electrode of the first transistor is electrically connected to a first control terminal a first voltage terminal the first node; a gate/first/second electrode of the second transistor is electrically connected to a second control terminal the first node a second voltage terminal; the display substrate also includes a first connection structure and a second connection structure arranged on the base substrate; the first transistor is connected to a part of the first connection structure; and/or, the second transistor is connected to a part of the second connection structure.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.

Abstract: The present disclosure relates to the field of pharmaceutical preparations, dosage regimens, and administration of an antibody-drug conjugate (ADC). More specifically, the ADC is composed of an anti-cadherin-6 (CDH6) antibody connected via a linker to an anticancer agent, such as topoisomerase I inhibitor.

Abstract: Capacitor cells are provided. A first PMOS transistor has a source connected to a power supply and a drain connected to a first node. A first NMOS transistor has a source connected to a ground and a drain connected to a second node. A second PMOS transistor has a source connected to the second node and a drain connected to the first node. A second NMOS transistor has a source connected to the ground and a drain connected to the first node. A first P+ doped region is shared by drains of the first and second PMOS transistors. A first gate metal is between the first P+ doped region and a second P+ doped region. A first N+ doped region is shared by sources of the first and second NMOS transistors. A second gate metal is between the first N+ doped region and a second N+ doped region.

Abstract: A method for fabricating a package structure is provided. The method includes premixing cellulose nanofibrils (CNFs) and a graphene material in a solvent to form a solution; removing the solvent from the solution to form a composite filler; mixing a prepolymeric material with the composite filler to form a composite material; and performing a molding process using the composite material.

Abstract: A decoder for decoding a codeword of a Tunstall code is provided, including: a sub-decoder configured to receive an input codeword of the Tunstall code to the decoder and output a decoded symbol of the input codeword: a symbol memory configured to receive and store the decoded symbol of the input codeword from the sub-decoder; and a controller configured to control the symbol memory to output one or more decoded symbols stored in the symbol memory.

Abstract: A focusing lens assembly includes a housing, a liquid lens, a solid lens assembly, an elastic member set, and a driving assembly. The liquid lens covers a light incidence port of the housing and includes an operating member. The solid lens assembly is located in an accommodating space of the housing. A liquid lens optical axis substantially coincides with the solid lens optical axis. The elastic member set is configured to suspend the solid lens assembly in the accommodating space. The driving assembly includes a coil set fixed to the solid lens assembly and a fixed magnet set fixed to the housing and corresponds to the coil set. When the coil set is driven, the coil set interacts with the fixed magnet set, so that the solid lens assembly moves along the solid lens optical axis to selectively enable the solid lens assembly to abut against the operating member.

Abstract: Provided display panel includes a first drive circuit including multiple shift registers. At least one shift register is a first-type shift register including pull-up unit, voltage storage unit, and first output unit. The pull-up unit is connected to first trigger terminal, first signal terminal, and first node. The voltage storage unit is connected to the first node, first clock terminal, second signal terminal, third signal terminal, fourth signal terminal, and second node. The first output unit is connected to the second node, the first clock terminal, and output terminal. During normal display scanning drive of the display panel, the display scanning drive can be interrupted when scanning to the first-type shift register, and the touch drive can be inserted and executed to realize the intra-frame touch drive which does not need to compress display time of one frame, has higher touch flexibility, facilitates improving touch effect and touch performance.

Abstract: A connection and a method of making a connection between an outer member and one or more inner structural members of a structure such as a building, the connection having a compression strut having an inner portion and an outer portion, the inner portion being supported by one of the one or more inner structural members, the outer portion being in contact with the outer member, a connector plate engaging the compression strut and the outer member and one or more tension fasteners attaching the connector plate to one or more of the one or more inner structural members.