Abstract: A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

Abstract: A display substrate includes a driving circuit arranged on a base substrate, the driving circuit includes a first node control circuit including a first transistor and a second transistor; a gate/first/second electrode of the first transistor is electrically connected to a first control terminal a first voltage terminal the first node; a gate/first/second electrode of the second transistor is electrically connected to a second control terminal the first node a second voltage terminal; the display substrate also includes a first connection structure and a second connection structure arranged on the base substrate; the first transistor is connected to a part of the first connection structure; and/or, the second transistor is connected to a part of the second connection structure.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a doped region in the substrate. The semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. The semiconductor device further includes a deep trench isolation (DTI) structure extending through the active area and between the emitter region and the collector region.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.

Abstract: The present disclosure relates to the field of pharmaceutical preparations, dosage regimens, and administration of an antibody-drug conjugate (ADC). More specifically, the ADC is composed of an anti-cadherin-6 (CDH6) antibody connected via a linker to an anticancer agent, such as topoisomerase I inhibitor.

Abstract: Capacitor cells are provided. A first PMOS transistor has a source connected to a power supply and a drain connected to a first node. A first NMOS transistor has a source connected to a ground and a drain connected to a second node. A second PMOS transistor has a source connected to the second node and a drain connected to the first node. A second NMOS transistor has a source connected to the ground and a drain connected to the first node. A first P+ doped region is shared by drains of the first and second PMOS transistors. A first gate metal is between the first P+ doped region and a second P+ doped region. A first N+ doped region is shared by sources of the first and second NMOS transistors. A second gate metal is between the first N+ doped region and a second N+ doped region.

Abstract: A method for fabricating a package structure is provided. The method includes premixing cellulose nanofibrils (CNFs) and a graphene material in a solvent to form a solution; removing the solvent from the solution to form a composite filler; mixing a prepolymeric material with the composite filler to form a composite material; and performing a molding process using the composite material.

Abstract: A decoder for decoding a codeword of a Tunstall code is provided, including: a sub-decoder configured to receive an input codeword of the Tunstall code to the decoder and output a decoded symbol of the input codeword: a symbol memory configured to receive and store the decoded symbol of the input codeword from the sub-decoder; and a controller configured to control the symbol memory to output one or more decoded symbols stored in the symbol memory.

Abstract: A focusing lens assembly includes a housing, a liquid lens, a solid lens assembly, an elastic member set, and a driving assembly. The liquid lens covers a light incidence port of the housing and includes an operating member. The solid lens assembly is located in an accommodating space of the housing. A liquid lens optical axis substantially coincides with the solid lens optical axis. The elastic member set is configured to suspend the solid lens assembly in the accommodating space. The driving assembly includes a coil set fixed to the solid lens assembly and a fixed magnet set fixed to the housing and corresponds to the coil set. When the coil set is driven, the coil set interacts with the fixed magnet set, so that the solid lens assembly moves along the solid lens optical axis to selectively enable the solid lens assembly to abut against the operating member.

Abstract: A connection and a method of making a connection between an outer member and one or more inner structural members of a structure such as a building, the connection having a compression strut having an inner portion and an outer portion, the inner portion being supported by one of the one or more inner structural members, the outer portion being in contact with the outer member, a connector plate engaging the compression strut and the outer member and one or more tension fasteners attaching the connector plate to one or more of the one or more inner structural members.

Abstract: Provided display panel includes a first drive circuit including multiple shift registers. At least one shift register is a first-type shift register including pull-up unit, voltage storage unit, and first output unit. The pull-up unit is connected to first trigger terminal, first signal terminal, and first node. The voltage storage unit is connected to the first node, first clock terminal, second signal terminal, third signal terminal, fourth signal terminal, and second node. The first output unit is connected to the second node, the first clock terminal, and output terminal. During normal display scanning drive of the display panel, the display scanning drive can be interrupted when scanning to the first-type shift register, and the touch drive can be inserted and executed to realize the intra-frame touch drive which does not need to compress display time of one frame, has higher touch flexibility, facilitates improving touch effect and touch performance.

Abstract: Devices, circuits, and methods for electrostatic discharge (ESD) protection are provided. An electrostatic discharge (ESD) protection circuit comprises a first transistor connected between a first voltage and a second voltage, and a first control circuit connected between the first voltage and the second voltage, and configured to supply a control signal to the first transistor. The circuit further comprises a second transistor connected between the second voltage and a third voltage, and a second control circuit connected between the second voltage and the third voltage, and configured to supply a control signal to the second transistor. The first control circuit and the second control circuit are connected to each other via a first interconnect and a second interconnect. The first and second transistors are configured to turn on in response to an ESD event.

Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.

Abstract: A method for fabricating a semiconductor device includes the steps of first defining a scribe line on a front side of a wafer, in which the wafer includes an inter-metal dielectric (IMD) layer disposed on a substrate and an alternating stack disposed on the IMD layer. Next, part of the alternating stack is removed to form a trench on the front side of the wafer, a dielectric layer is formed in the trench, and then a dicing process is performed along the scribe line from a back side of the wafer to divide the wafer into chips.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.

Abstract: A display panel and a display apparatus are provided. The display panel includes an array substrate; a color film substrate; support pillars; pixel sub-units; and data lines. The support pillars include a primary support pillar and auxiliary support pillars. The primary support pillar and the auxiliary support pillars each include a first support pillar. The pixel sub-units are formed by crossing the scan lines and the data lines. The pixel sub-units each include a thin film transistor and a pixel electrode. The thin film transistor includes a gate, a source and a drain. The scan line is electrically connected to the gate. The data line is electrically connected to the source. The pixel electrode is electrically connected to the drain. The present disclosure can enhance supporting capacity of the display panel.

Abstract: Capacitor cells are provided. A first PMOS transistor is coupled between a power supply and a first node, and has a gate directly connected to a second node. A first NMOS transistor is coupled between a ground and the second node, and has a gate directly connected to the first node. A second PMOS transistor is coupled between the second node and the power supply, and has a gate directly connected to the second node. A second NMOS transistor is coupled between the first node and the ground, and has a gate directly connected to the first node. Sources of the first and second NMOS transistors share an N+ doped region in the P-type well region. The first NMOS transistor is disposed between the second NMOS transistor and the first and second PMOS transistors. Source of the first PMOS transistor is directly connected to the power supply.

Abstract: A photographing method and an electronic device. The photographing method includes: receiving, by the electronic device, a first operation for triggering the electronic device to enter a large aperture mode; obtaining, by the electronic device, a distance value between the electronic device and a photographed target object in response to the first operation; enabling, by the electronic device in a case that a distance value does not exceed a first distance threshold, a first camera and a second camera to acquire the image of the target object; enabling, by the electronic device in a case that the distance value exceeds the first distance threshold, the first camera and a third camera to acquire the image of the target object; and displaying, by the electronic device, a preview image including the target object.

Abstract: Aspects concern a. method for controlling a transport system comprising determining, for first score adjustment vectors, allocation rates, fulfilment rates and gains of fulfilled predetermined transport tasks. The method further comprises determining a second score adjustment vector from the allocation rates, fulfilment rates and gains determined for the first score adjustment vectors by estimating the second score adjustment vector to maximize a gain of fulfilled requested transport tasks subject to a predetermined minimum allocation rate of requested, transport tasks of each transport task category and a predetermined minimum fulfilment rate of requested transport tasks of each transport task category.