Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a doped well in the substrate, wherein the doped well comprises a first concentration of dopants of a first type in the substrate. The semiconductor device further includes a doped region in the substrate, wherein the doped region comprises a second concentration of the dopants of the first type, the doped region extends around the doped well, and the doped region is electrically insulated from the doped well. The semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. The semiconductor device further includes a deep trench isolation (DTI) structure extending through the active area and between the emitter region and the collector region.

Abstract: An electrostatic discharge (ESD) protection cell region (of a semiconductor device) includes a resistor-diode ladder and a power clamp circuit coupled in parallel between a first power rail PR1 and a second power rail PR2. The resistor-diode ladder is also coupled between an input/output (I/O) pad of the semiconductor device and core circuitry of the semiconductor device. The resistor-diode ladder includes: a first diode coupled between a first node and the first power rail; a first resistor coupled between the first node and a second node; a second diode coupled between the second node and the first power rail; a third diode coupled between the first node and the second power rail; and a fourth diode coupled between the second node and the second power rail. The first node is coupled to the I/O pad. The resistor-diode ladder is coupled between the I/O pad and the core circuitry.

Abstract: A method of manufacturing a snapback electrostatic discharge (ESD) protection circuit includes fabricating a first well in a substrate, the first well extending in a first direction, and having a first dopant type, fabricating a drain region of a transistor in the first well, the drain region having a second dopant type, fabricating a source region of the transistor in the first well, the source region extending in the first direction, having the second dopant type, and being separated from the drain region in a second direction, fabricating a second well in the first well, the second well extending in the first direction, having the second dopant type, and being adjacent to a portion of the drain region, and fabricating a gate region of the transistor, the gate region being between the drain region and the source region, and being over the first well and the substrate.

Abstract: A crankshaft simulation device includes: a fixed shaft in which a through hole extending in the axial direction of the fixed shaft is provided; a wedge-shaped rod which is movable in the through hole under an external force, and the first end of the wedge-shaped rod is extendable from the first axial end of the fixed shaft, the second end of the wedge-shaped rod is extendable from the second axial end of the fixed shaft, and the first end of the wedge-shaped rod is provided with an inclined surface so that the first end of the wedge-shaped rod is wedge-shaped; a support rod extending from the first axial end of the fixed shaft in the axial direction of the fixed shaft; a movable shaft in which a flat through hole is provided, and the support rod is inserted into the flat through hole, and the size of the flat through hole in the radial direction of the movable shaft is configured to allow the movable shaft to be shifted in the radial direction of the movable shaft, and the flat through hole is configured to a

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: A method of manufacturing an integrated circuit (IC) device includes forming, over a substrate, at least one first well region of a first semiconductor type, and a second well region of a second semiconductor type different from the first semiconductor type. The method further includes forming a plurality of first doped regions of the first semiconductor type over the at least one first well region, and a second doped region of the second semiconductor type over the second well region. Each of the plurality of first doped regions has a first length in a first direction. The second doped region extends in the first direction between at least two first doped regions among the plurality of first doped regions over a second length greater than the first length.

Abstract: A method of making a semiconductor device includes manufacturing lines extending in a first direction over doped zones in a substrate, wherein each of the lines has a line width measured along a first direction. The method further includes trimming the lines into line segments having ends over an isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the first direction, and the line width is substantially similar to the gate electrode width.

Abstract: A connection and a method of making a connection between an outer member and one or more inner structural members of a structure such as a building, the connection having a compression strut having an inner portion and an outer portion, the inner portion being supported by one of the one or more inner structural members, the outer portion being in contact with the outer member, a connector plate engaging the compression strut and the outer member and one or more tension fasteners attaching the connector plate to one or more of the one or more inner structural members.

Abstract: Examples of the present application disclose a semiconductor device and a fabrication method thereof and a memory system. The semiconductor device includes: a stack structure including first regions and second regions; channel structures that are located in the first regions and penetrate through the stack structure along a first direction; and gate line isolation structures that are located in the second regions and extend along a second direction, wherein the gate line isolation structures penetrate through the stack structure along the first direction and are in a concavo-convex shape along a third direction.

Abstract: A display panel and a display apparatus are provided. The display panel includes an array substrate; a color film substrate; support pillars; pixel sub-units; and data lines. The support pillars include a primary support pillar that includes a first support pillar. The pixel sub-units are formed by crossing the scan lines and the data lines. The pixel sub-units each include a thin film transistor and a pixel electrode. The thin film transistor includes a gate, a source and a drain. The scan line is electrically connected to the gate. The data line is electrically connected to the source. The pixel electrode is electrically connected to the drain. The present disclosure can enhance supporting capacity of the display panel.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a first chip, a second chip and a conductive structure. The first chip has an active side and an opposite side disposed opposite to each other. The second chip includes a chip bonding portion and an outer pad, and the outer pad is located outside the chip bonding portion. The first chip is disposed on the chip bonding portion of the second chip with the active side. The conductive structure is disposed on the outer pad, and the conductive structure includes a stack of a plurality of metal balls. The stack extends from the outer pad beyond the opposite side of the first chip.

Abstract: A semiconductor device includes a device wafer including a first side and a second side opposite to each other, and a carrier wafer disposed over the first side of the device wafer. The carrier wafer includes an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first diode and a second diode. The first diode is operatively coupled to a first power rail, and the second diode is operatively coupled to a second power rail at least through the device wafer.

Abstract: Systems and methods are provided for a self-biasing electro-static discharge (ESD) power clamp. The ESD power clamp comprises an ESD detection circuit coupled to a positive supply voltage node and a ground voltage node. The ESD detection circuit includes a first node having a first voltage level during a standby mode and a second voltage level during an ESD mode. The ESD power clamp further comprises a discharge circuit coupled to the ESD detection circuit that includes a plurality of discharge elements a self-biasing node having a third voltage level during the standby mode. The third voltage level provides a voltage drop across at least one of the discharge elements that is less than the first voltage level. The discharge circuit provides a high-impedance path during the standby mode and a low-impedance path during the ESD mode.

Abstract: A device includes a first circuit region including a nanostructure device and a second circuit region offset from the first circuit region. The nanostructure device has a vertical stack of nanostructures disposed in a plurality of first semiconductor layers and a gate structure wrapping around the nanostructures of the vertical stack. The second circuit region includes a bipolar junction device electrically connected to the nanostructure device and at least one diode electrically connected between a collector and a base of the bipolar junction device. At least one implant region extends through the plurality of first semiconductor layers and a plurality of second semiconductor layers that are disposed between respective vertically neighboring pairs of the plurality of first semiconductor layers. A backside interconnect structure is electrically connected to a source/drain region of the nanostructure device.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

Abstract: A method of making a semiconductor device includes manufacturing doped zones in a first semiconductor material over a substrate. The method further includes forming an isolation structure between adjacent doped zones of the first semiconductor material. The method further includes manufacturing lines extending in a first direction over the doped zones of the first semiconductor material, wherein each of the lines has a line width measured along a second direction perpendicular to the first direction. The method further includes trimming the lines into line segments having ends over the isolation structure. The method further includes etching a transistor gate electrode over the substrate, wherein transistor gate electrode has a gate electrode width measured along the second direction, and wherein the line width is substantially similar to the gate electrode width.

Abstract: A gate driving unit and a driving method for the same, a shift register circuit, and a display apparatus, and an operating period of the gate driving unit comprises a first and a second sub-period; a first pull-down node control module in the gate driving unit causes a first pull-down sub-node to be at an inactive level in the second sub-period, and causes the first pull-down sub-node to be at an active level during a reset phase in the first sub-period; a second pull-down node control module causes a second pull-down sub-node to be at an inactive level in the first sub-period, and causes the second pull-down sub-node to be at an active level during a reset phase in the second sub-period. It is possible to shorten the turn-on time of transistors controlled by the first and the second pull-down sub-nodes, and improve the reliability of the gate driving unit.

Abstract: A diode structure includes a silicon remaining layer, a first p-type doping region disposed on the silicon remaining layer and a first n-type doping region disposed on the silicon remaining layer. A first channel region is disposed on the silicon remaining layer and between the p-type doping region and the n-type doping region, wherein the first channel region, the first p-type doping region, and the first n-type doping region are disposed along a first direction.

Abstract: A cabin monitoring and situation understanding perceiving method is proposed. A cabin interior image capturing step is performed to capture a cabin interior image. A generative adversarial network model creating step is performed to create a generative adversarial network model according to the cabin interior image. An image adjusting step is performed to adjust the cabin interior image to generate an approximate image. A cabin interior monitoring step is performed to process the approximate image to generate a facial recognizing result and a human pose estimating result. A cabin exterior image and voice capturing step is performed to capture a cabin exterior image and a voice information. A situation understanding perceiving step is performed to process at least one of the approximate image, the cabin exterior image and the voice information according to a situation understanding model to perceive a situation understanding result.