Abstract: A battery pack includes: a plurality of battery cells, each including a negative electrode and a positive electrode, the positive and negative electrodes being arranged on a same side of the battery cell; a substrate arranged on the plurality of battery cells and including a first surface and a second surface located on opposite sides of the substrate, and a through hole exposing the negative electrode and the positive electrode of each of the plurality of battery cells; a first conductive plate arranged on the first surface of the substrate and including a first hole; and a second conductive plate arranged on the second surface of the substrate and including a second hole.

Abstract: Provided is a reactor capable of improving the symmetry of the profile of a thin film deposited on a substrate with an asymmetric exhaust structure, wherein a distance between a gas flow control ring (FCR) and an exhaust unit on one side where an exhaust port is located is greater than a distance between the FCR and the exhaust unit on the opposite side of the exhaust port.

Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.

Abstract: The present disclosure provides a phototransistor and a manufacturing method therefor, the phototransistor having a defective oxide ray absorption layer introduced to an oxide semiconductor phototransistor through a solution process or a defective oxide ray absorption part introduced to an interface between a gate insulation film and an oxide semiconductor layer through interface control, which forms damage, thereby improving light absorption in the range of a visible light region.

Abstract: Battery packs and methods for controlling charging of battery packs are disclosed. In one aspect, a battery pack includes a battery including at least one battery cell, a first pack terminal and a second pack terminal configured to be connected to a charger, and a discharging switch including a first switch and a diode. The first switch is connected between the second pack terminal and the battery. The diode is connected in parallel to the first switch and has a forward direction in which charging current of the battery flows. The battery pack further includes a battery management unit configured to select a charging mode from one of a first charging mode in which the battery is charged with charging current flowing through the first switch and a second charging mode in which the battery is charged with charging current flowing through the diode.

Abstract: An electronic device is disclosed. The electronic device comprises: a housing; and a pattern region formed on at least a portion of the surface of the housing. The pattern region includes a first edge, a second edge, and a first pattern formed between the first edge and the second edge. The first pattern includes a first floor portion, a first valley portion and a second valley portion which are positioned closer than the first floor portion to the inner space of the housing, and a first inclined surface extending from the first floor portion to the first valley portion and the second valley portion. The first floor portion may be formed in a first color, and the first inclined surface may be formed in a second color.

Abstract: A method for generating an image that includes at least one of a vignette effect or a grain effect corresponding to an input image may include obtaining the input image including at least one of the vignette effect or the grain effect; identifying at least one of a vignette parameter or a grain parameter of the input image; obtaining at least one of a vignette filter based on the vignette parameter or a grain layer based on the grain parameter; and generating the image that includes at least one of the vignette effect or the grain effect by applying at least one of the vignette filter or the grain layer to the image.

Abstract: The inventive concept provides a method for guiding an inspection of a large intestine by using an endoscope, being performed by an apparatus, including receiving an image captured by the endoscope introduced into a large intestine of a patient, in real time, recognizing each of section images containing at least one wrinkle in the large intestine, in the image, displaying a first visual effect of representing the wrinkle in each of the section images, determining whether a rear surface of the wrinkle in each of the section images is photographed, and displaying a second visual effect of representing, in at least one of the section images, in which a rear surface of a wrinkle has not been photographed, that the rear surface of the wrinkle in the at least one of the section images has not been photographed.

Abstract: Devices and techniques are generally described for using user feedback to determine routing decisions in a speech processing system. In various examples, first data representing a first utterance may be received. Second data representing a first semantic interpretation of the first utterance may be determined. A first intent data processing application may be selected for processing the second data. Feedback data may be determined related to the first intent data processing application processing the second data. Third data representing a semantic interpretation of a second utterance may be received, wherein the first semantic interpretation is the same as the second semantic interpretation. A second intent data processing application may be determined for processing the third data based at least in part on the feedback data.

Abstract: A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.

Abstract: An electronic device is provided. The electronic device includes a camera module, a sensor module, at least one processor configured to be operatively connected to the camera module and the sensor module, and a memory configured to be operatively connected to the at least one processor.

Abstract: A method of encoding a three-dimensional (3D) image including a point cloud includes grouping a plurality of points included in the point cloud into at least one segment; generating patches by projecting the points included in the segment onto a predetermined plane in a first direction or a second direction; generating two-dimensional (2D) images by packing the patches; and generating and outputting a bitstream including information about a direction in which each point is projected to generate the patches and information about the 2D images.

Abstract: A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.

Abstract: A method for analyzing vulnerabilities may include: an analysis target URL receiving step of receiving a plurality of analysis target uniform resource locator (URL) addresses extracted from the analysis target server; an identification key setting step of setting respective identification keys corresponding to the plurality of analysis target URL addresses; a vulnerability analyzing step of performing a simulated attack so as to access the external server by the analysis target server by inserting an analysis hypertext transfer protocol (HTTP) request sentence including a URL address of an external server and the identification key into the analysis target URL address; an access record checking step of requesting an access record of the analysis target server to the external server; and a vulnerability extracting step of extracting a vulnerability of the analysis target server by using the identification key included in the access record.

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

Abstract: The electronic device, comprises a communication circuitry configured to exchange data with an external electronic device; a first processor configured to exchange data with the external electronic device via the communication circuitry; a second processor configured to control the communication circuitry; and a memory configured to store priority information for each path characteristic of paths established over a network, wherein a first one of the first processor and the second processor is configured to: identify at least one priority information mapped to the path characteristic information based on the priority information in the memory; and store priority related information based on the at least one priority information, and wherein a second one of the first processor and the second processor is configured to: transmit data corresponding to the service identification information to the first one of the first processor and the second processor based on the priority related information.

Abstract: A clock buffer that uses low-to-medium quality factor (e.g., QF of 2 to 5) inductors in shunt-series and in series-shunt configuration in high-speed clock distribution stages. Shunt-series and series-shunt inductors extend amplifier bandwidth. Applying shunt-series and series-shunt inductors to high-speed clock distribution filters jitter, attenuates supply noise, and improves fanout. An asymmetric multiplexer with inductors in shunt or in shunt-series configurations. Another asymmetric multiplexer with capacitively coupled tri-stateable inverter-based buffer stages. These two multiplexer techniques along with the ability to ‘hide’ a load of a non-preferred path at a virtual ground node of the shunt inductor, the multiplexer improves the jitter and power consumption of the preferred path significantly. A de-multiplexer (DeMux) is also shown using inductors. A combination of a shunt-multiplexer and an inductor-based DeMux is also discussed.

Abstract: Provided are methods and systems for video recording. The video recording method may include capturing a preview image, using a camera included in the electronic device, based on a set frame rate and in response to the electronic device entering an image photographing mode; storing the captured preview image; applying at least one time-fake effect among a plurality of set time-fake effects to the stored preview image; and creating a video file of a set format by encoding the preview image after the applying the at least one time-fake effect.

Abstract: A battery pack including a plurality of battery cells; and a rigid printed circuit board (PCB) electrically connected to each battery cell and extending across the plurality of battery cells, wherein the rigid PCB includes a bus to electrically connect the plurality of battery cells to each other, and a battery management system (BMS) to control a charge/discharge operation of the plurality of battery cells.