Abstract: The present invention relates to a lens and a camera module comprising same. A lens according to one embodiment of the present invention comprises: an optical part constituting an optical surface of the lens; a flange part formed on the periphery of the optical part; a first cutting part formed on one side of the flange part; and a second cutting part formed on the other side of the flange part, wherein the first cutting part and the second cutting part may be formed to form angles which are perpendicular to each other with respect to the central axis of the optical part. Accordingly, it is possible to reduce a lens shape error which occurs when assembling a lens, and prevent a decrease in the resolution of the lens.

Abstract: The present disclosure relates to a spin head, apparatus and method for treating a substrate including the spin head. The spin head includes a supporting plate where a substrate is placed and a chuck pin placed on the supporting plate and supporting a lateral portion of the substrate, wherein the chuck pin includes an outer body and an inner body inserted in the outer body and provided with a different material from the outer body, wherein each outer body and the inner body is provided with any one of a first material or a second material, and wherein one material of the first material and the second material is provided with a material having lower heat conductivity and better thermal resistance than another one.

Abstract: A light emitting element that includes a first electrode, a first hole transport region on the first electrode, a first emission layer on the first hole transport region, a first electron transport region on the first emission layer, and a second electrode on the first electron transport region is provided.

Abstract: The disclosure provides a display device and a method of manufacturing the display device. The display device includes a first electrode disposed on an organic insulating layer and a second electrode disposed on an intermediate layer and overlapping the first electrode and an auxiliary electrode in a plan view, the second electrode electrically contacting the auxiliary electrode through a hole of the intermediate layer. A thickness of the intermediate layer varies in a direction away from a center of the hole of the intermediate layer.

Abstract: A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 ?m to 100 ?m, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.

Abstract: A battery pack includes at least one battery cell having first and second end portions spaced apart from each other in a length direction of the at least one battery cell, and an outer peripheral surface between the first and second end portions, a circuit board connected to the at least one battery cell, the circuit board to monitor the at least one battery cell, and a sensor extending from the circuit board toward the at least one battery cell, the sensor contacting the outer peripheral surface of the at least one battery cell, and the sensor having a casing having a first surface that is concave toward the outer peripheral surface of the at least one battery cell, a thermistor chip inside the casing, a lead wire extending from the thermistor chip outside the casing, and a filler inside the casing.

Abstract: A nonvolatile memory device includes a memory cell array in a first semiconductor layer and including a first memory cell connected to a first word line and a first bit line and a second memory cell connected to the first word line and a second bit line; a page buffer circuit in a second semiconductor layer and including a first page buffer connected to the first bit line, and a second page buffer connected to the second bit line; and a page buffer controller in the second semiconductor layer. The page buffer controller controls the first and second page buffers so that a develop timing of a first sensing node of the first page buffer is different from a develop timing of a second sensing node of the second page buffer. The first page buffer is closer to a through electrode region than the second page buffer.

Abstract: A battery pack including a cell block including a group of battery cells electrically connected to each other; and a detector on a lateral surface of the cell block, the detector including an insulative body, a voltage detection lead, and a temperature detection lead, wherein the insulative body faces an outer peripheral surface of a first battery cell, the outer peripheral surface being exposed at the lateral surface of the cell block, and the voltage detection lead and the temperature detection lead are at least partially surrounded and fixed by the insulative body.

Abstract: A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.

Abstract: A semiconductor device including a stack structure including gate stack and dummy stack regions; a vertical memory structure penetrating through the gate stack region; and a first vertical dummy structure penetrating through a portion of the dummy stack region, wherein the gate stack region includes interlayer insulating and gate layers alternately and repeatedly stacked on each other, the dummy stack region includes dummy insulating and dummy horizontal layers alternately and repeatedly stacked on each other, at least one of the dummy horizontal layers and the gate layers include materials different from each other, an upper surface of the vertical memory structure is at a higher level than an upper surface of the first vertical dummy structure, and a lowermost dummy upper horizontal layer at a higher level than the first vertical dummy structure overlaps the first vertical dummy structure.

Abstract: An offset detector circuit includes a digital signal register storing M unit digital signals received in latest M signal periods, M being a natural number, among digital signals generated based on a single-ended PAM-N signal, N being an odd number, a comparator outputting a comparison signal of a pair of signals included in differential signals generated from a differential signal generator based on the single-ended PAM-N signal, a comparison result register storing M unit comparison signals corresponding to the latest M signal periods among the comparison signals, a pattern detector outputting a detection signal when the M unit digital signals match a predetermined signal pattern, and an offset checker checking patterns of the M unit comparison signals in response to the detection signal, and outputting an offset detection signal when the patterns of the M unit comparison signals match a predetermined offset pattern.

Abstract: A traffic optimization module includes a profile management component and a data restructuring component, wherein the traffic optimization module is configured to receive, from the UPF, context information that is based on a traffic for a data packet being processed; update traffic history information stored in the profile management component based on the context information; determine whether to perform data restructuring that is based on the traffic history information or not by referring to the traffic history information stored in the profile management component; identify a profile that at least matches a target profile requested by the data restructuring component from among the plurality of profiles; restructure a data set included in the identified profile as a data set including data required for processing the context information; and provide the identified profile including the restructured data set to the profile management component.

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material.

Abstract: According to an aspect of the inventive concept, there is provided a die-to-wafer bonding structure including a die having a first test pad, a first bonding pad formed on the first test pad, and a first insulating layer, the first bonding pad penetrates the first insulating layer. The structure may further include a wafer having a second test pad, a second bonding pad formed on the second test pad, and a second insulating layer, the second bonding pad penetrates the second insulating layer. The structure may further include a polymer layer surrounding all side surfaces of the first bonding pad and all side surfaces of the second bonding pad, the polymer layer being arranged between the die and the wafer. Additionally, the wafer and the die may be bonded together.

Abstract: According to an embodiment of the present disclosure, an electronic device comprises: a camera; a display; a memory; and at least one processor electrically connected to the display and the memory. The processor obtains an input of selecting a first image, generates a color filter by comparing the first image and a second image having a color pattern different from the first image, obtains a third image, and generates a fourth image by applying the generate color filter to the third image. The processor derives a function by comparing color values of pixels of the first image and the second image, and coefficients of the function. The color filter may include the function derived by comparing the first image and the second image, the coefficients of the function, and a color lookup table generated on the basis of the derived function. The processor stores the generated color filter in the memory and generates the fourth image by applying the stored color filter to the third image.

Abstract: An organic light-emitting device and display apparatus, the device including a first electrode; a second electrode facing the first electrode; an emission layer between the first and second electrode; a hole control layer between the first electrode and the emission layer; and an electron control layer between the emission layer and the second electrode, wherein the emission layer includes a plurality of sub-emission layers to emit light having different wavelengths, at least portions of the plurality of sub-emission layers do not overlap one another, the plurality of sub-emission layers include: a first sub-emission layer including a first color light-emitting dopant, and a second sub-emission layer including a second color light-emitting dopant, the first and second sub-emission layers each include a hole-transporting and electron-transporting host which form an exciplex, and a triplet energy of the exciplex is equal to or greater than triplet energies of the first and second color light-emitting dopant.

Abstract: A light-emitting device includes a first electrode; a second electrode facing the first electrode; m emission units between the first electrode and the second electrode; and m?1 charge-generating unit(s) between adjacent ones of the emission units, where m is a natural number of 2 or more. The emission units each include an emission layer. At least one of the charge-generating unit(s) includes an n-type charge-generating layer and a p-type charge-generating layer; and the n-type charge-generating layer includes a first material and a second material. The first material includes an organic electron transport compound; and the second material includes at least one selected from an alkali metal, an alkali metal alloy, an alkaline earth metal, an alkaline earth metal alloy, a lanthanide metal, and a lanthanide metal alloy. The light-emitting device may have improved hole and electron balance, a decreased driving voltage, and excellent efficiency and/or lifespan characteristics.

Abstract: For a display device having a plurality of subpixels disposed in an active area of a display panel, a method for processing a compensation data of the display device may include reconfiguring an order of unit patches having the compensation data so that the unit patches having similar reference values are positioned adjacent to each other when the compensation data are compressed. The disclosed method can improve the compression process efficiency where a compression loss can be reduced, and an effect of an image quality improvement using the compensation data can be enhanced.

Abstract: A light-emitting device includes a second electrode that includes: a first layer including a first metal having a work function with an absolute value of 5.2 eV or less and a second metal having an electrical conductivity of 1×107 S/m or more; and a second layer consisting of the second metal having the electrical conductivity of 1×107 S/m or more. The first metal and the second metal are different from each other, a thickness of the first layer is from 1 ? to 30 ?, and a thickness of the second layer is from 10 ? to 110 ?.

Abstract: A light emitting element includes a first electrode, a hole transport region disposed on the first electrode, an emission layer disposed on the hole transport region, an electron transport region which is disposed on the emission layer and includes an electron transport layer and an electron injection layer disposed on the electron transport layer, and a second electrode disposed on the electron transport region, wherein the electron injection layer includes a host represented by Formula A or Formula B, and a metal dopant, and the metal dopant includes Ag, Bi, Mg, Li, Yb, Cu, La, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, or Lu, thereby improving electron injection characteristics and having excellent or suitable luminous efficiency.